Indian Institute of Technology Roorkee
29th June - 2nd July 2017

Invited Talks
Subhasish Mukherjee,
Cadence India

Subhasish Mukherjee has been leading the Design for Test (DFT) R&D group of Cadence India for 12 years. He is the key architect of several DFT features like Scan insertion and connection, Core testing conforming to IEEE 1500 standard, Boundary scan architecture, Compression techniques, Physically aware scan, Smartscan and 3D DFT flow for Cadence Synthesis and Test products. He has received multiple Cadence internal awards for his contributions. 

He has co-authored and presented multiple papers in Asian Test Symposium, International Test Conference, VLSI conference and served as session chair in ATS. He has co-authored papers in journals like Future Fab International. He also presented multiple papers in Cadence internal conferences.  

Prior to joining Cadence, he worked at Motorola, USA. Subhasish received M.E. in Computer Science and Engineering from Jadavpur University, Kolkata in 1997.

TITLE OF TALK: SmartScan – Hierarchical Test Compression for Pin-Limited Low Power Designs

Abstract of the talk:
 Reducing the cost of testing a chip is one of the major focus areas in DFT. Complex System on Chip designs impose additional complexities that requires to be solved. 

The talk presents Smartscan, a technique aimed to provide test compression with fewer test pins, enable pattern reuse, provide hierarchical test methodologies, address test power issues due to high scan switching and thus reducing the overall test cost.

Sudarshan Kumar,
VP of Technology, HSMC

Sudarshan Kumar has 31 years of industry experience in custom and ASIC design. In Intel he was responsible for several high performance microprocessor designs, including Pentium(R) and Itanium(R) families of microprocessors. He managed Low power Design Technology(LPDT) in Intel, where he developed several low power solutions and helped reduce power in various microprocessors. Presently as the VP of Technology, HSMC, he is responsible for several innovative low power & high performance solutions such as low power memories and flops, Low power TCAMs, high speed IP blocks, crossbars for networking products and high speed data compression IP. He has done B.Tech from IIT Kharagpur and MS from Washington State University, USA. He has received 30+ US patents. 

TITLE OF TALK: Techniques to reduce dynamic power.
Abstract of the talk:
 Power and power density has become a significant issue in any silicon chip design and manufacturing. They affect cost, weight, portability and reliability. There has been very high profile product failure due to high power consumption. While both component of power, namely static and dynamic power contribute to the problem, it is dynamic power that creates most of the problems. Dynamic power is application dependent and difficult to measure. It also creates power supply noise issues(di/dt). In this presentation, some of techniques to reduce dynamic power will be presented. These techniques are above and beyond what is being done in the industry to reduce dynamic power.
Vice President & India Country Manager, NXP

Sanjay Gupta is the Vice President and India Country Manager at NXP India Pvt. Ltd. Sanjay is responsible for leading NXP’s business in India and ensuring local compliance with government and corporate programs and policies. He also leads Methodology, Quality and Culture for the Automotive Microcontrollers & Processors (AMP) R&D in the organization. He is also the Chairperson for Innovation board (Methodology, flows and tools) for BU Automotive across organizational units. He is leading three diverse R&D locations (Noida, Bangalore and Hyderabad) consisting of nearly 1,800 employees representing all NXP product groups 
Sanjay had started his professional journey with Motorola in 1996 and has worked on assignments in the Wireless business, Digital Networking, Industrial MCU and the automotive organizations. He holds multiple U.S. patents in the areas of state retention within a data processing system and miller cap tolerant special clock tree elements. Sanjay earned his earned his bachelor’s degree in engineering in electronics and communication from Delhi College of Engineering, and his MBA from the Indian School of Business – Hyderabad.

TITLE OF TALK: Automotive Innovations for future.
Masahiro Fujita,
VLSI Design and Education Center 
The University of Tokyo

Masahiro Fujita received his Ph.D. in Information Engineering from the University of Tokyo in 1985 on his work on model checking of hardware designs by using logic programming languages. In 1985, he joined Fujitsu as a researcher and started to work on hardware automatic synthesis as well as formal verification methods and tools, including enhancements of BDD/SAT-based techniques. From 1993 to 2000, he was director at Fujitsu Laboratories of America and headed a hardware formal verification group developing a formal verifier for real-life designs having more than several million gates. The developed tool has been used in production internally at Fujitsu and externally as well. Since March 2000, he has been a professor at VLSI Design and Education Center of the University of Tokyo. He has done innovative work in the areas of hardware verification, synthesis, testing, and software verification-mostly targeting embedded software and web-based programs. He has been involved in a Japanese governmental research project for dependable system designs and has developed a formal verifier for C programs that could be used for both hardware and embedded software designs. The tool is now under evaluation jointly with industry under governmental support. He has authored and co-authored 10 books, and has more than 200 publications. He has been involved as program and steering committee member in many prestigious conferences on CAD, VLSI designs, software engineering, and more. His current research interests include synthesis and verification in SoC (System on Chip), hardware/software co-designs targeting embedded systems, digital/analog co-designs, and formal analysis, verification, and synthesis of web-based programs and embedded programs.
TITLE OF TALK: To be updated soon.
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