Indian Institute of Technology Roorkee
29th June - 2nd July 2017

IIT Roorkee in association with IEEE UP Section and VLSI Society of India presents
21st International Symposium on VLSI Design and Test
 (VDAT 2017)
29th JUNE - 2nd JULY 2017
IIT Roorkee, INDIA
Fellowship applications are invited. Please visit Fellowships for more information.
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VLSI Design and test VDAT is a flagship event of the VLSI Society of India. This Symposium follows successful organization of twenty symposiums in previous years. VDAT -2017 is being organized at Indian Institute of Technology Roorkee, India. In true sense, VDAT-2017 is a focused research event encompassing themes related to various disciplines of VLSI. The objective of the symposium is to bring professional engineers, academicians and research scholars of matching interests on a common platform to share new ideas, experiences, and knowledge in various fields of VLSI Design, Test and Technology. The scientific program will consist of peer-reveiwed paper presentations in parallel technical sessions. In addition, keynote lectures, presentation by industry professionals, panel discussions, tutorials and poster presentation will be conducted during the conference. Such interactions will faciliate better understanding about technological developments all across the globe amongst the peers. This conference will certainly ignite the minds of the researchers for undertaking more interdisciplinary collaborative research for up gradation of technology.
P. Chakrabarti  
Professor, IIT BHU

TOPIC: Organic Semiconductor Devices: Potential and Challenges

Maryam Shojaei Baghini  
Professor, IIT Bombay

TOPIC: Circuit structures, trade-offs and design optimization in CMOS signal conditioning circuits for personal healthcare.

Devesh Dwivedi  
Deputy Director  
ASIC Product Development 
GlobalFoundries, India  

TOPIC: To be updated soon.


Accepted Tutorials
Following is the list of accepted tutorials for VDAT 2017. All tutorials will be half-day (3-4 hours) and will be conducted in parallel during the conference, 29th June - 2nd July 2017. Please make sure to indicate the tutorial you will attend during registration.

Tutorial #1:  “Achieving the Best STA Accuracy for Advanced Nodes”
By: Gauri Sankar Malla, Synopsys India Pvt. Ltd., India

Tutorial #2:  "Advanced Analog Design"
By: HS Jatana, SCL Chandigarh, India

Tutorial #3: "Design of Modern mm-Wave Transmitters and Power Amplifiers in Silicon and FD SoI CMOS"
By: Dr. Bhattacharya

Tutorial #4:"Computational Lithography for Advanced CMOS Nodes" 
By: Nihar Ranjan Mohapatra, IIT Gandhinagar

Tutorial #5:  "Transaction Level Modelling with System C For System Level Design"
By: Nishit Gupta, Microelectronics Development Division, Ministry of Communication and Information Technoogy, Govt. of India

Tutorial #6: "Circuit and System Design Issues for IoT Sensor Node"
By: M. Hasan, AMU, Aligarh, India.
Registrations are open.
Please Note: IEEE/ VSI Student members are encouraged to participate and a 20% concession is being given to them. Apart from this, Fellowships will be given to deserving candidates.

Last date for registration is 10th June 2017.

Regular Paper

Last Date for Paper Submission : 27th Feb, 2017  4th April 2017 (CLOSED)  
Notification of Acceptance          : 15th May, 2017  18th May, 2017
Camera Ready Version                : 10th May, 2017  25th May, 2017


Tutorial Proposal                   :15th Mar, 2017  30th March 2017 (CLOSED)
Tutorial Announcement               :15th Apr, 2017 4th May 2017

Work-in-progress (WIP) Forum
WIP Submission                       : 5th Mar, 2017  30th March 2017 (CLOSED)
Notification of Acceptance          : 15th May, 2017  
Camera Ready Version                : 25th Apr, 2017 20th May, 2017


Companies are invited to become Sponsors of the International Symposium on VLSI Design and Test VDAT 2017.