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Manhas, Sanjeev
Sanjeev Manhas Associate Professor samanfec[at]iitr.ac.in +91-1332-285147
Areas of Interest
  • Nanoscale devices and circuits, Nanowire MOSFET modeling and circuit design
  • 3D NAND , Performance Enhancement of NAND Memories
  • MEMs, Cantilever based MEMs and applications
  • Reliability, MOS device reliability
  • Nano scale DRAM, Novel Techniques for Improving Refresh and Reliability
  • Sensors, CNT based sensors
  • Nanofabrication, Nanoscale CMOS process and VLSI technologies
Professional Background
FromToDesignationOrganisation
2014To dateAssociate Professor IIT Roorkee
20082014Assistant ProfessorIIT Roorkee
20072008Senior Research EngineerInstitute of Microelectronics, Singapore
20032007Member Technical StaffMicron(Tech Semiconductor) Technology, Singapore/USA
20022003Research FellowDe Montfort University, Leicester, UK
Educational Details
DegreeSubjectUniversityYear
Ph. D.Electronics and Electrical EngineeringDe Montfort University, Leicester, UK2003
M. Tech.Solid State TechnologyIIT Madras1996
Sponsored Research Projects
TopicFunding AgencyYear
Si Nanowire CMOS for Ultra High Density CircuitsFIG2009
Investigation of Silicon nanowire FET reliability and its modelingDST2012
Design and Development of Carbon Nanotubes Based Chemical SensorDRDO2011
Implementation of TIDE scheme for Entrepreneurship DevelopmentMeitY 2016
Scheme of Financial Assistance for setting up of Electronics and ICT Academies, DeitYMeitY 2016
Establishment of TBI at IIT RoorkeeDST2017
FIST (Profilometer and PECVD systems for Microelectronics Lab) DST2016
Development of microfluidics based device to detect CTCsSMILE 2017
Memberships
  • IEEE Electron Device Society, Member
  • IEEE Solid State Circuits Society, Member
PHDs Supervised
TopicScholar NameStatus of PHDRegistration Year
Analysis of Si-nanowire GAA MOSFET and its Implementation in Logic DesignGaurav KaushalA2008
Performance Models for Nanoscale VLSI CircuitsBaljit KaurA2009
Vertical Nanowire Based CMOS Circuit DesignMaheshwaram SatishA2010
Carbon Nanotube Interconnects for VLSIManoj Kumar MajumderA2010
Concurrent Multi-band Oscillators for Multifunctional Wireless SystemsL SnehalathaO2011
Silicon Nanowire Based Circuit Design and NBTI ReliabilityOm PrakashO2013
Fabrication and Characterization of Vibrational Energy Harvesters Sandeep Singh ChauhanO2013
Carbon Nanotube Devices for Sensor ApplicationsNarendra KumarO2014
Charge Trap Based SONOS/MONOS Devices for 3D NAND Flash Memory ApplicationsUpendra Mohan BhattO2014
Design, Analysis and Optimization of DRAM TransistorSatendra Kumar GuatamO2015
Reliability of Gallium-Nitride Based High Electron Mobility Transistors and Circuits Sourabh JindalO2015
Nanomaterials Based Biosensors for detection of pathogens and Small MoleculesPardeep KumarO2015
Refereed Journal Papers
  1. S. K. Manhas, M. M. De Souza, A. S. Oates, “Quantifying the Nature of Hot Carrier Degradation in the Spacer Region of LDD nMOSFETs,” IEEE Transactions on Device and Materials Reliability, vol. 1, no. 3, p. 134, Sept. 2001.
  2. M. M. De Souza, J. Wang, S. Manhas, E. M. Sankara Narayanan, A.S. Oates, “A Comparison of Early Stage Hot Carrier Degradation Behaviour in 5 and 3 V Sub-micron Low Doped Drain Metal Oxide Semiconductor Field Effect Transistors,” Microelectronics Reliab., Vol. 44, No. 2, p. 169, Feb. 2001.
  3. S. K. Manhas, D. Chandra Sehkar, A. S. Oates M. M. De Souza, “Characterisation of Series Resistance Degradation through Charge Pumping Technique”, Microelectronics Reliab., Vol. 43, p. 617, 2003.
  4. M. M. De Souza, S. K. Manhas, D. Chandra Sekhar, A. S. Oates, P. Chaparala, “Influence of Mobility model on extraction of stress dependent source-drain series resistance”, Microelectronics Reliability, 25, Vol 44, Jan 2004.
  5. G. Cao, S. K. Manhas, E.M.S. Narayanan, M. M. De Souza, D. Hinchley, “Comparative study of drift region designs in RF LDMOSFETs”, IEEE Trans Electron Devices, Vol 51,  Issue 8,  Aug. 2004, 1296 – 1303.
  6. N Singh, K D. Buddharaju, S. K. Manhas, A. Agarwal, S C. Rustagi, G. Q. Lo, N. Balasubramanian, “Si, SiGe Nanowire Devices by Top–Down Technology and Their Applications,” IEEE Transactions on Electron Devices, Vol. 55, No. 11, p. 3107, 2008.
  7. S. K. Manhas, N. Singh, G. Q. Lo, “Barrier Layer Thickness Analysis for Reliable Copper Plug Process in CMOS Technology”, Microelectronic Reliability, Vol. 51, Issue 8, 1365-1371, August 2011.
  8. Satish Maheshwaram, S. K. Manhas, Gaurav Kaushal, Bulusu Anand, Navab Singh, “Vertical Silicon Nanowire Gate All Around Field Effect Transistor Based Nanoscale CMOS,” IEEE Electron Device Letters, 32 (8), pp. 1011-1013, August 2011.
  9. Deepika Agarwal, G. Nagendra Babu, B. K. Kaushik, and S. K. Manhas, “Design of Low Complexity Encoder for Capacitively Coupled VLSI Interconnects,” IJCA Special Issue on Evolution in Networks and Computer Communications, Vol. 2, No. 8, Oct. 2011, pp. 45-49.          
  10. Manoj Kumar Majumder, B. K. Kaushik and S. K. Manhas, “A Comparative Analysis of Single Walled CNT Bundle and Multi Walled CNT as Future Global VLSI Interconnects” International Journal of Computer Applications,” (2) 32-38, October, 2011.
  11. Gaurav Kaushal, S. S. Rathod, Satish Maheshwaram, S. K. Manhas, A. K. Saxena, and S. Dasgupta, “Radiation Effects in Si-NW GAA FET and CMOS Inverter: A TCAD Simulation Study,” IEEE Trans. Electron Devices, vol. 59, pp. 1563-1566, May 2012.
  12. M. K. Majumder, N. D. Pandya, B. K. Kaushik, and S. K. Manhas, “Dynamic crosstalk effects in mixed CNT bundle interconnects”, IET Electronics Letters, vol. 48, no. 7, pp. 384-385, 29 March, 2012.
  13. M. K. Majumder, N. D. Pandya, B. K. Kaushik, and S. K. Manhas, "Analysis of MWCNT and Bundled SWCNT Interconnects: Impact on Crosstalk and Area," IEEE Electron Device Letters, vol. 33, pp. 1180- 1182, 2012.
  14. S. Maheshwaram, S. K. Manhas, G. Kaushal, B. Anand and N. Singh, "Device Circuit Co-Design Issues in Vertical Nanowire CMOS Platform",  IEEE Electron Device Lett., vol.33, no. 7, pp.934-936, July 2012.
  15. G. Nagendra Babu, Deepika Agarwal, B.  K.  Kaushik, and S.  K.  Manhas, “Bus Encoder for Crosstalk Avoidance in RLC Modeled Interconnects,” International journal of VLSI design & Communication Systems (VLSICS), vol. 3, no. 1, pp. 181-191, Feb. 2012.
  16. Manoj Kumar Majumder, Nisarg D. Pandya, B. K. Kaushik, and S. K. Manhas, “Signal Integrity Analysis in Single and Bundled Carbon Nanotube Interconnects,” Journal of Nanoscience, vol. 2013, Article ID 407301, 6 pages, 2013.
  17. Gaurav Kaushal, S. K. Manhas, Satish Maheshwaram, S. Dasgupta, Bulusu Anand, Navab Singh, “Tuning Source/Drain Extension Profile for Current Matching in Nanowire CMOS Logic,” IEEE Trans on Nanotechnology, Vol. 11, No. 5, p. 1033 Sept. 2012.
  18. Shejale Kiran Prakash, Harjeet Singh, Himanshu Panjiar, Sanjeev Manhas, B S S Daniel, “Application of Graphene Oxide and TiO2 in the fabrication of Dye sensitized solar cells module by electrode modification”, Advanced Materials Research Vol. 585, p. 255, 2012.
  19. G. Kaushal, S. K. Manhas, S. Maheshwaram, S. Dasgupta, “Impact of series resistance on Si nanowire MOSFET performance,” Journ., Comput Electron, Vol. 12, p. 306, 2013.
  20. Satish Maheshwaram, S. K. Manhas, Gaurav Kaushal, Bulusu Anand, and Navab Singh,”Vertical Nanowire CMOS Parasitic Modeling and its Performance Analysis,” IEEE Trans Electron Dev vol. 60, No. 9, p. 2943 2013.
  21. A Kumar, V Kumar, S Agarwal, A Basak, N Jain, A Bulusu, SK Manhas, “Nitrogen-Terminated Semiconducting Zigzag GNR FET With Negative Differential Resistance,” IEEE Trans. Nanotechnology, vol. 13, pp 16 - 22, 2014.
  22. Archana Pandey, Swati Raycha, Satish Maheshwaram, Sanjeev K Manhas, Sudeb Dasgupta, Ashok K Saxena, Bulusu Anand, “Effect of Load Capacitance and Input Transition Time on FinFET Inverter Capacitances,” IEEE Trans. Electron Dev, Vol. 61, pp 30-36, 2014.
  23. Saurabh K Nema, M SaiKiran, P Singh, Archana Pandey, SK Manhas, AK Saxena, Anand Bulusu, “Improved Underlap FinFET with Asymmetric Spacer Permittivities,” Physics of Semiconductor Devices, Springer International Publishing, pp. 267-268, 2014.
  24. Neeraj Jain, S Manhas, AK Aggarwal, PK Chaudhry, “Effect of Metal Contact on CNT Based Sensing of NO2 Molecules,” Physics of Semiconductor Devices, Springer International Publishing, pp. 637-639, 2014.
  25. Ravi Shankar, G. Kaushal, S. Maheshwaram, S. Dasgupta, S. K. Manhas, “A Degradation Model of Double Gate and Gate-All-Around MOSFETs With Interface Trapped Charges Including Effects of Channel Mobile Charge Carriers,” IEEE Trans. Material and Device Reliability, Vol. 14, No. 2, p. 689, 2014.
  26. G. Kaushal, S. K. Manhas, Satish Maheshwaram, Bulusu Anand, Sudeb Dasgupta, and Navab Singh, “Novel Design Methodology Using LEXT Sizing in Nanowire CMOS Logic,” IEEE Trans. On Nanotechnology, Vol. 13, No. 4, pp. 650-658, 2014.
  27. Ashish Joshi, Satinder Sharma, Sanjeev Manhas, and S. Dasgupta, “A Switch-Capacitor DAC Successive Approximation ADC Using Regulated Clocked Current Mirror,” International Journal of Electronics and Electrical Engineering, Vol. 2, No. 1, pp. 50-55, 2014.
  28. Baljit Kaur, Naushad Alam, S. K. Manhas, and Bulusu Anand, “Efficient ECSM Characterization Considering Voltage, Temperature, and Mechanical, Stress Variability,” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, Nov, 2014.
  29. Ashish Joshi, S.K. Manhas, Satinder K. Sharma, S. Dasgupta, “An 8 bit, 100 kS/s, switch-capacitor DAC SAR ADC for RFID applications,” Microelectronics Journal, Vol. 46, Issue 6, pp 453–46, June 2015.
  30. Gaurav Kaushal, H. Jeong, Satish Maheshwaram, S.K. Manhas, S. Dasgupta, S.O. Jung, “Low power SRAM design for 14 nm GAA Si-nanowire technology,” Microelectronics Journal 46 (2015) 1239–1247. 
  31. Archana Pandey, Harsh Kumar, S. K. Manhas, Sudeb Dasgupta, and Bulusu Anand, “Atypical Voltage Transitions in FinFET Multistage Circuits: Origin and Significance,” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 63, NO. 3, MARCH 2016, p 1392.
  32. Baljit Kaur, Arvind Sharma, Naushad Alam, S. K. Manhas, Bulusu Anand, “A variation aware timing model for a 2-input NAND gate and its use in sub-65nm CMOS standard cell characterization,” Microelectronics Journal, Volume 53, July 2016, Pages 45–55.
  33. Snehalatha Lalithamma · Nagendra Prasad Pathak · Sanjeev Kumar Manhas “Design and analysis of vee dipole based reconfigurable planar antenna,” Progress In Electromagnetics Research Letters 70:123-128, January 2017.
  34. Om Prakash, Swen Beniwal, Satish Maheshwaram, Anand Bulusu, Navab Singh, S. K. Manhas, “Compact NBTI reliability modeling in Si nanowire MOSFETs and effect in circuits,” IEEE Transactions on Device and Materials Reliability, PP(99):1-1, April 2017.
  35. Om Prakash, Satish Maheshwaram, Mohit Sharma, Anand Bulusu, and Sanjeev K. Manhas, “ Performance and Variability Analysis of SiNW 6T-SRAM Cell using Compact Model with Parasitics,” IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 16, NO. 6, P. 965, NOVEMBER 2017.