- Circuit Design, Variation aware VLSI circuit design methodology
- Delay Models, Delay and timing models for VLSI circuits
- VLSI Devices, Novel device/circuit co-design methodologies
- MIxed-Signal Design, Low Voltage CMOS VCO Design and Modeling
- Circuit Design, Near Threshold Circuit Design
|2006||2007||Sr. Research Engineer||IIT Bombay|
|2007||2008||Sr. Design Engineeer||Freescale Semiconductor India (Earstwhile Semiconductor Division of Motorola Inc.)|
|2008||2014||Assistant Professor||IIT Roorkee|
|2014||Present||Associate Professor||IIT Roorkee|
|2013||On going||Faculty Advisor||IEEE CAS Student Chapter, IIT Roorkee|
|2014||On going||Branch Counsellor||IEEE Student Branch|
|Robust Methodology for Nanoscale VLSI Circuit Design Considering Layout Dependent Variatiations||DST||2013|
|Nanoscale FinFET Device and Circuit Design Methodology||DST||2009|
|Chips to Systems Design (SMDP)||DIETY||2015|
- IEEE Circuits and Systems Society, Member
- IEEE Electron Device Society, Member
- IEEE Solid State Circuits Society, Member
|Title||Course Code||Class Name||Semester|
|Fundamentals of Microelectronics||EC 344||UG||Spring|
|Analog Circuits||EC 205||UG||Autumn|
|Digital VLSI Circuit Design||EC 544||PG + UG||Spring|
|Semiconductor Devices||EC 142||U.G.||Spring|
|Analog VLSI Design||EC 558||P.G.||Spring|
|Analog Electronics||EC 301||U.G.||Autumn|
|Fundamentals of Electronics||EC 102||U.G.||Spring|
|Topic||Scholar Name||Status of PHD||Registration Year|
|Near Threshold CMOS Digital Circuit Design and Analysis||Inder Chaudhary||O||2014|
|Low Voltage CMOS VCO Design||Lalit Dani||O||2015|
|CMOS PLL Design||Neeraj Mishra||O||2016|
|FinFET Device-Circuit interaction (Analog Domain)||Shashank Bancchor||O||2015|
|Tunnel FET Device-Circuit Interaction||Abhishek Acharya||O||2015|
|Mechanical Stress Aware Nanoscale VLSI Circuit Design Methodologies||Arvind Sharma||O||2013|
|FinFET device-circuit interaction in low-voltage domain||Sarita Yadav||O||2016|
|Modeling of FinFET device parasitics||Archana Pandey||O||2012|
|TunnelFET device-circuit co-design||Menaka||A||2010|
|Device-circuit co-design of Silicon Nanowire transistor||Satish Maheshwaram||A||2010|
|Performance models for nanoscale VLSI circuits||Baljit Kaur||A||2010|
|Robust circuit design methodology for nanoscale VLSI technologies||Naushad Alam||A||2009|
|Couse Name||Sponsored By||Date|
|Design Issues in Nanoscale VLSI Circuits and Systems||QIP||June 2010|
|FinFET Logic Gate Capacitances: Impact of Circuit Level Parameters||IEEE Indicon 2013, IIT Bombay||14.12.13|
|FinFET Device Circuit Co-Design: Issues and Challenges||IEEE VLSI Design Conference 2015, Bangalore||04.01.2015|
|Nanoscale VLSI Circuit Design: Timing Issues and Solutions||NITTTR, Chandigarh||09.10.2016|
|Process variation aware Standard Cell extraction||Freescale Semiconductor India Pvt. Ltd.||PG|
|Tunnel FET Device Modeling||ST Microelectronics||PG|
|CMOS VCO Design||ST Microelectronics||PG|
|High Speed Circuits||Global Foundries||PG|
- Abhishek Acharya, Sudeb Dasgupta and Bulusu Anand, “A Novel VDSAT Extraction Method for Tunnel FETs and Its Implication on Analog Design,” IEEE Transactions on Electron Devices, pp. 629-623, February 2017.
- Arvind Sharma, Naushad Alam, Sudeb Dasgupta, Bulusu Anand, “Multifinger MOSFETs’ Optimization Considering Stress and INWE in Static CMOS Circuits”, IEEE Transactions on Electron Devices, PP, no. 99, 2016.
- Baljit Kaur, Arvind Sharma, Naushad Alam, Sanjeev K. Manhas, Bulusu Anand, “A Variation Aware Timing Model for a 2-Input NAND Gate and Its Use in Sub-65nm CMOS Standard Cell Characterization”, Microelectronics Journal (Elsevier), vol. 53, pp. 45-55, 2016.
- Archana Pandey; Harsh Kumar; S. K. Manhas; Sudeb Dasgupta; Bulusu Anand , “Atypical Voltage Transitions in FinFET Multistage Circuits: Origin and significance” , IEEE Transactions on Electron Devices, pp. 1392-1396, march 2016.
- Baljit Kaur, Naushad Alam, S. K. Manhas, Bulusu Anand, “Efficient ECSM characterization considering voltage, temperature and mechanical stress variability,” Accepted for publication in IEEE Transactions on Circuits and Systems – I, October 2014.
- Gaurav Kaushal, S. K. Manhas, S. Maheshwaram, S. Dasgupta, B. Anand, and N. Singh, “Novel Design Methodology Using Lext Sizing in Nanowire CMOS Logic” IEEE Transactions on Nanotechnology, pp. 650-658, July 2014.
- Naushad Alam, Bulusu Anand and Sudeb Dasgupta, “An Analytical Delay Model for Mechanical Stress Induced Systematic Variability Analysis in Nanoscale Circuit Design,” IEEE Transactions on Circuits and Systems -I, pp. 1714-1726, June 2014.
- Archana Pandey, Swati Raycha, Satish Maheshwaram, S. K. Manhas, S. Dasgupta, Bulusu Anand, “Effect of Load Capacitance and Input Transition Time on Underlap FinFET Capacitance,” IEEE Transactions on Electron Devices, pp. 30-36, January 2014.
- Ashwani Kumar, Vishvendra Kumar, Bulusu Anand, S. Manhas, “Nitrogen-Terminated Semiconducting Zigzag GNR FET With Negative Differential Resistance,” IEEE Transactions on Nanotechnology, pp. 16-22, January 2014.
- Menka, Bulusu Anand and Dasgupta S., “Two Dimensional Analytical Modeling for Asymmetric 3T and 4T Double Gate Tunnel FET in Subthreshold Region: Potential and Electric Field”, Elsevier Microelectronics Journal, pp. 1251-1259, December 2013.
- S. Maheshwaram, S. K. Manhas, G. Kaushal, B. Anand and N. Singh, “Vertical Nanowire CMOS Parasitic Modeling and its Performance Analysis,” IEEE Transactions on Electron Devices, vol. 60, no. 9, pp. 2943-2950, September 2013.
- N. Alam, B. Anand, and S. Dasgupta, “The Impact of Process-Induced Mechanical Stress in Narrow Width Devices and Variable Taper CMOS Buffer Design", Elsevier Microelectronics Reliability, vol. 53, Issue 5, pp. 718-724, May 2013.
- N. Alam, B. Anand, and S. Dasgupta, “The Impact of Process-Induced Mechanical Stress on CMOS Buffer Design using Multi-Fingered Devices", Elsevier Microelectronics Reliability, vol. 53, Issue 3, pp. 379-385, March 2013.
- N. Alam, B. Anand, and S. Dasgupta, "Gate-Pitch Optimization for Circuit Design using Strain-Engineered Multi-Finger Gate Structures", IEEE Transactions on Electron Devices, vol. 59, no. 11, pp. 3120-3123, November 2012.
- Gaurav Kaushal, S. Manhas, S. Maheshwaram, S. Dasgupta, A. Bulusu and N. Singh, “Tuning source/drain extension profile in current matching in nanowire CMOS logic,” IEEE Transactions in Nanotechnology, vol. 11, no. 5, pp. 1033-1035, September 2012.
- Satish Maheshwaram, S. K. Manhas, G. Kaushal, B. Anand and N. Singh, "Device Circuit Co-Design Issues in Vertical Nanowire CMOS Platform," IEEE Electron Device Letters, vol.33, no. 7, pp.934-936, July 2012.
- Satish Maheshwaram, S. K. Manhas, Gaurav Kaushal, Bulusu Anand, and Navab Singh, “Vertical Silicon Nanowire Gate-All-Around Field Effect Transistor Based Nanoscale CMOS,” IEEE Electron Device Letters, pp. 1011-1013, August 2011.
- Pradeep Kumar Chawda, B. Anand, V. Ramgopal Rao, “Optimum Body Bias constraints for leakage reduction in high-K Complementary Metal Oxide Semiconductor Circuits,” Japanese Journal of Applied Physics (JJAP), May 2009.
- Bulusu Anand, M. P. Desai, and V. Ramgopal Rao, "Silicon Film Thickness Optimization for SOI-DTMOS from Circuit Performance considerations", IEEE Electron Device Letters, pp. 436-438, June 2004.
- P. Sivaram, B. Anand, M. P. Desai, “Silicon film thickness considerations for SOI-DTMOS,” IEEE Electron Device Letters, pp. 276-278, May 2002.
Selected Publications in International Conferences:
- Chaudhry Indra Kumar, A. Sharma, S. Miryala, Bulusu Anand, "A novel energy-efficient self-correcting methodology employing INWE," IEEE SMACD, 2016.
- Sayyaparaju Sagar Varma, A. Sharma, Bulusu Anand, "An efficient methodology to characterize the TSPC flip flop setup time for static timing analysis," IEEE SMACD, 2016.
- Archana Pandey, Harsh Kumar, Praanshu Goyal, S. K. Manhas, Sudeb Dasgupta, Bulusu Anand “FinFET Device Circuit Co-design Issues: Impact of Circuit Parameters on Delay” , IEEE VLSI Design, 2016.
- Arvind Sharma, Neeraj Mishra, Naushad Alam, Sudeb Dasgupta, and Bulusu Anand, "Pre-layout Estimation of Performance and Design of Basic Analog Circuits in Stress Enabled Technologies" in IEEE VDAT, 2015.
- Yogesh Chaurasiya, Surabhi Bhargava, Arvind Sharma, Baljit Kaur, and Bulusu Anand, "Timing Model for Two Stage Buffer and Its Application in ECSM Characterization", in IEEE VDAT, 2015.
- A. Sharma, Y. Sharma, S. Dasgupta, and B. Anand, “Efficient Static D-Latch Standard Cell Characterization Using a Novel Setup Time Model”, IEEE ISQED-2015.
- Parmanand Singh,V. Asthana, R. Sithanandam, A. Bulusu, S. Dasgupta, “Analytical Modeling of Sub-onset Current of Tunnel Field Effect Transistor,” IEEE VLSI Design, 2014.
Bijay Kumar Dalai, A. Bulusu, N. Kannan and Arvind Kumar Sharma, "An Empirical Delta Delay Model for Highly Scaled CMOS Inverter Considering Well Proximity Effect," VDAT 2014.
Saurabh K. Nema, M. SaiKiran, P. Singh, Archana Pandey, S. K. Manhas, A. K. Saxena, Anand Bulusu, “Improved Underlap FinFET with Asymmetric Spacer Permittivities,” Accepted in IWPSD 2013.
S. Maheshwaram, S.K. Manhas, G. Kaushal, and B. Anand, “Vertical Nanowire MOSFET Parasitic Resistance Modeling,” in Proc. IEEE EDSSC 2013, Hong Kong.
Menka, Bulusu Anand and Dasgupta S., “A TCAD approach to evaluate channel electrondensity of double gate symmetric n-tunnel FET”, INDICON 2012, pp:577-581.
Baljit Kaur, S. Miryala, S. K. Manhas and Bulusu Anand, “An Efficient Method for ECSM Characterization of CMOS Inverter in Nanometer Range Technologies,” Accepted in IEEE International Symposium on Quality Electronic Design (ISQED) 2013.
Archana Pandey, Swati Raycha, Satish Maheshwaram, S. K. Manhas, S. Dasgupta, Bulusu Anand, “Underlap FinFET Capacitance: Impact of Input Transition Time and Output Load” IEEE International Nanoelectronics Conference (INEC) 2013.
N. Alam, B. Anand, and S. Dasgupta, “Process induced mechanical stress aware poly-pitch optimization for enhanced circuit performance”, in IEEE ISQED, 2012, pp. 717-720.
N. Alam, B. Anand, and S. Dasgupta, “Impact of Dummy Poly on the Process-Induced Mechanical Stress Enhanced Circuit Performance", in VDAT 2012, pp. 357-359.
N. Alam, S. Dasgupta, and B. Anand “Impact of process-induced mechanical stress on multi-fingered device performance”, in Proc. IWPSD, 2011.
Arnab Kumar Biswas, Anand Bulusu and Sudeb Dasgupta, “A Proposed Output Buffer at 90 nm Technology with Minimum Signal Switching Noise at 83.3MHz,” Proceedings of IEEE ISVLSI 2011.
Sandeep Miryala, Baljit Kaur, Bulusu Anand and Sanjeev Manhas, "Efficient Nanoscale VLSI Standard Cell Library Characterization Using a Novel Delay Model," Proceedings of IEEE ISQED 2011.
Saurabh Nema, Mayank Srivastava, Angada B. Sachid, A. K. Saxena, Anand Bulusu, "A Novel Scaling Strategy for Underlap FinFETs," 2010, IIT Kharagpur.
Bulusu Anand, V. Ramgopal Rao and M. P. Desai, "Circuit Performance Improvement Using PDSOI-DTMOS Devices with a Novel Optimal Sizing Scheme Considering Body Parasitics,” Accepted in VLSI-DAT, 2007.
Pradeep Kumar Chawda, B. Anand, and V.Ramgopal Rao, "Effectiveness of Optimum Body Bias for Leakage Reduction in High K CMOS Circuits", Proceedings of 35th International Conference on Solid State Devices and Materials (SSDM 2004), pp. 434-435, Tokyo, Japan, September 15-17, 2004.
Sushant Suryagandh, B. Anand, M. P. Desai and V. Ramgopal Rao, “Dynamic Threshold Voltage CMOS (DTMOS) for Future Low Power Sub-1V Applications," Proceedings of 10th International Workshop on Physics of Semiconductor Devices (IWPSD), pp. 655-658, December 1999, New Delhi.
- Bulusu Anand, Shivananda Reddy, Surya Veeraraghavan, “A Method to Find Sensitivity of Standard Cells to Process/Model Changes,” Defensive Publication of Freescale Semiconductor Inc., June 2008, http://www.priorartdatabase.com/IPCOM/000172383/
- S. K. Manhas, S. Nema, A. Bulusu, “A method of fabricating dual/asymmetric dielectric constant (dual-K) spacers in MOSFET,” application no. CINIITR000100017, 2012 (Provisional Indian Patent).
- I give letters of recommendation to only the following: 1. My BTP or M.Tech dissertation students. 2. Students who did a project with me: Only PhD or MS leading to PhD applications. 3. Students who secured at least a 9 (B+) in my course(s): Only PhD or MS leading to PhD applications.