Employees Alumni Placements Students International Relations
Visitors
हिन्दी संस्करण
Language Option
Spotlight
Faculty Profiles
Faculty Search Committee
Prospective Faculty
Important Contacts
Prospective Students
RICET
EICT
SMDP
Room Booking System[Internal Use]
Manhas, Sanjeev
Sanjeev Manhas Professor samanfec[at]iitr.ac.in +91-1332-285147
Areas of Interest
  • Nanoscale Devices and Circuits:, Nanowire MOSFET Modeling and Circuit Design
  • Memories:, NVM and AI Applications, 3D NAND, nanoscale DRAM
  • MEMs:, MEMS Based Sensors and Energy Harvesting
  • Reliability:, CMOS Reliability- BTI, TDDB
  • Sensors:, CNT Based Sensors, Novel ISFET Devices
  • Nanofabrication:, Nanoscale CMOS Process and VLSI Technologies
Professional Background
FromToDesignationOrganisation
2019To dateProfessorIIT Roorkee
20142019Associate Professor IIT Roorkee
20082014Assistant ProfessorIIT Roorkee
20072008Senior Research EngineerInstitute of Microelectronics, Singapore
20032007Member Technical StaffMicron Technology, Singapore/USA
Educational Details
DegreeSubjectUniversityYear
Ph. D.Electronics and Electrical EngineeringDe Montfort University, Leicester, UK2003
M. Tech.Solid State TechnologyIIT Madras1996
Administrative Background
FromToDesignationOrganisationLevel
20152019Faculty-in-Charge, TIDES Business IncubatorIIT Roorkee
20152017Chairman, Departmental Faculty Research CommitteeIIT Roorkee
20162018Chairman, Departmental Academic Programme Committee (DAPC)IIT Roorkee
20152019Faculty-in-Charge, STEPIIT Roorkee
Sponsored Research Projects
TopicFunding AgencyYear
FeFET TCAD for Interface EngineeringApplied Materials, USA2019
Non-filamentary three-Terminal Memristor Architecture for Bio-mimetic and Logic Design MHRD (SPARC)2019
TCAD for DRAM and 3D NANDApplied Materials, USA2018
DIC PhD FellowshipDIC2018
Implementation of TIDE Scheme for Entrepreneurship DevelopmentMeitY 2015
Scheme of Financial Assistance for Setting up of Electronics and ICT Academies, DeitYMeitY 2016
Establishment of Technology Business Incubator at IIT RoorkeeDST2017
Investigation of Silicon Nanowire FET Reliability and its ModelingDST2012
FIST (Profilometer and PECVD systems for Microelectronics Lab) DST2016
Development of Microfluidics Based Device to Detect CTCsSMILE 2017
Design and Development of Carbon Nanotubes Based Chemical SensorDRDO2011
Si Nanowire CMOS for Ultra High Density CircuitsFIG2009
Memberships
  • IEEE Electron Device Society, Member
  • IEEE Solid State Circuits Society, Member
Teaching Engagements
TitleCourse CodeClass NameSemester
Fundamentals of MicroelectronicsEC 344UGSpring
Analog CircuitsEC 205UGAutumn
Semiconductor DevicesEC242UGAutumn
Analog ElectronicsEC 205UGAutumn
Fundamentals of ElectronicsEC 102UGAutumn
MOS Device PhysicsEC 571PGAutumn
VLSI TechnologyEC 555PGSpring
Nanoscale TransistorsEC 587PGSpring
Digital CircuitsEC 203UGAutumn
Compound Semiconductor DevicesEC 559PGSpring
Technology of Nanostructured FabricationNT 511PGAutumn
PHDs Supervised
TopicScholar NameStatus of PHDRegistration Year
Analysis of Si-nanowire GAA MOSFET and its Implementation in Logic DesignGaurav KaushalA2008
Performance Models for Nanoscale VLSI CircuitsBaljit KaurA2009
Vertical Nanowire Based CMOS Circuit DesignMaheshwaram SatishA2010
Carbon Nanotube Interconnects for VLSIManoj Kumar MajumderA2010
Concurrent Multi-band Oscillators for Multifunctional Wireless SystemsL SnehalathaA2011
Silicon Nanowire Based Circuit Design and NBTI ReliabilityOm PrakashA2013
Fabrication and Characterization of Vibrational Energy Harvesters Sandeep Singh ChauhanO2013
Carbon Nanotube Devices for Sensor ApplicationsNarendra KumarO2014
Charge Trap Based SONOS/MONOS Devices for 3D NAND Flash Memory ApplicationsUpendra Mohan BhattO2014
Design, Analysis and Optimization of DRAM TransistorSatendra Kumar GuatamO2015
Reliability of Gallium-Nitride Based High Electron Mobility Transistors and Circuits Sourabh JindalO2015
Nanomaterials Based Biosensors for detection of pathogens and Small MoleculesPardeep KumarO2015
Refereed Journal Papers

Selected Publications 

 

  1. N. Kumar, N. K. Navani, and S. K. Manhas, “Altering the Schottky Barrier Height and Conductance by Using Metal Nanoparticles in Carbon Nanotubes-Based Devices,” IEEE Trans. Electron Devices, vol. 66, no. 6, pp. 2789–2794, 2019, doi: 10.1109/TED.2019.2908526.  
  2. S. K. Gautam, S. K. Manhas, A. Kumar, M. Pakala and E. Yieh, "Row Hammering Mitigation Using Metal Nanowire in Saddle Fin DRAM," in IEEE Transactions on Electron Devices (Published , July 2019.)  doi: 10.1109/TED.2019.2931347     
  3. Sandeep Singh Chauhan, M.M Joggler, S.K. Manhas, "High Power Density CMOS Compatible Micro- machined MEMs Energy Harvester" IEEE Sensor Journal, (Published as an early access in IEEE explore, June 2019.)
  4. S. K. Gautam, A. Kumar, and S. K. Manhas, "Improvement of Row Hammering Using Metal Nanoparticles in DRAM—A Simulation Study,” IEEE Electron Device Letters, vol. 39, pp. 1286-1289, 2018.
  5. S. S. Chauhan, M. Joglekar, and S. K. Manhas, "Influence of Process Parameters and Formation of Highly c-Axis Oriented AlN Thin Films on Mo by Reactive Sputtering," IEEE/TMS Journal of Electronics Material, Vol. 47, no. 12, pp-7520-7530, 2018.
  6. S. S. Chauhan, M. Joglekar, and S. K. Manhas, "Fabrication of Cantilever MEMs structure of C-axis Grown AlN film for Energy Harvester Application," Proc EEE International Conference on Industrial Technology (ICIT), Lyon, France, vol. 300, p. 200, 2018.
  7. U. M. Bhatt, A. Kumar, and S. K. Manhas, "Performance Enhancement by Optimization of Poly Grain Size and Channel Thickness in a Vertical Channel 3-D NAND Flash Memory,"  IEEE Transactions on Electron Devices, vol. 65, pp. 1781-1786, 2018.
  8. O. Prakash, S. Maheshwaram, M. Sharma, A. Bulusu, and S. K. Manhas, "Performance and Variability Analysis of SiNW 6T-SRAM Cell Using Compact Model With Parasitics,” IEEE Transactions on Nanotechnology, vol. 16, pp. 965-973, 2017.
  9. O. Prakash, S. Beniwal, S. Maheshwaram, A. Bulusu, N. Singh, and S. Manhas, "Compact NBTI Reliability Modeling in Si Nanowire MOSFETs and Effect in Circuits,"  IEEE Transactions on Device Materials Reliability, vol. 17, pp. 404-413, 2017.
  10. A. Pandey, H. Kumar, S. Manhas, S. Dasgupta, and B. Anand, "Atypical Voltage Transitions in FinFET Multistage Circuits: Origin and Significance," IEEE Transactions on Electron Devices, vol. 63, pp. 1392-1396, 2016.
  11. A. Joshi, S. Manhas, S. K. Sharma, and S. Dasgupta, "An 8 bit, 100 kS/s, switch-capacitor DAC SAR ADC for RFID applications," Microelectronics Journal, vol. 46, pp. 453-461, 2015.
  12. R. Shankar, G. Kaushal, S. Maheshwaram, S. Dasgupta, and S. Manhas, "A degradation model of double gate and gate-all-around MOSFETs with interface trapped charges including effects of channel mobile charge carriers," J IEEE transactions on Device Materials Reliability, vol. 14, pp. 689-697, 2014.
  13. A. Pandey, S. Raycha, S. Maheshwaram, S. K. Manhas, S. Dasgupta, A. K. Saxena, and B. Anand, "Effect of load capacitance and input transition time on FinFET inverter capacitances," J IEEE Transactions on Electron Devices, vol. 61, pp. 30-36, 2014.
  14. M. K. Majumder, B. K. Kaushik, and S. K. Manhas, "Analysis of delay and dynamic crosstalk in bundled carbon nanotube interconnects," IEEE Transactions on Electromagnetic Compatibility, vol. 56, pp. 1666-1673, 2014.
  15. A. Kumar, V. Kumar, S. Agarwal, A. Basak, N. Jain, A. Bulusu, and S. Manhas, "Nitrogen-terminated semiconducting zigzag GNR FET with negative differential resistance," IEEE Transactions on Nanotechnology, vol. 13, pp. 16-22, 2014.
  16. G. Kaushal, S. Manhas, S. Maheshwaram, B. Anand, S. Dasgupta, and N. Singh, "Novel Design Methodology Using Lext Sizing in Nanowire CMOS Logic," IEEE Transactions on Nanotechnology, vol. 13, pp. 650-658, 2014.
  17. B. Kaur, N. Alam, S. Manhas, and B. Anand, "Efficient ECSM Characterization Considering Voltage, Temperature, and Mechanical Stress Variability," IEEE Trans. on Circuits Systems, vol. 61, pp. 3407-3415, 2014.
  18. N. Jain, S. Manhas, A. Aggarwal, and P. Chaudhry, "Effect of metal contact on CNT based sensing of NO2 molecules," in Physics of Semiconductor Devices, ed: Springer, Cham, 2014, pp. 637-639.
  19. S. Maheshwaram, S. Manhas, G. Kaushal, B. Anand, and N. Singh, "Vertical nanowire CMOS parasitic modeling and its performance analysis," IEEE Transactions on Electron Devices, vol. 60, pp. 2943-2950, 2013.
  20. M. K. Majumder, N. D. Pandya, B. Kaushik, and S. Manhas, "Analysis of MWCNT and bundled SWCNT interconnects: Impact on crosstalk and area," IEEE Electron Device Letters, vol. 33, pp. 1180-1182, 2012.
  21. S. Maheshwaram, S. Manhas, G. Kaushal, B. Anand, and N. Singh, "Device circuit co-design issues in vertical nanowire CMOS platform," IEEE Electron Device Letters, vol. 33, pp. 934-936, 2012.
  22. G. Kaushal, S. Manhas, S. Maheshwaram, S. Dasgupta, B. Anand, and N. Singh, "Tuning source/drain extension profile for current matching in nanowire CMOS logic," IEEE Transactions on Nanotechnology, vol. 11, pp. 1033-1039, 2012.
  23. S. Manhas, N. Singh, and G. Lo, "Barrier layer thickness analysis for reliable copper plug process in CMOS technology," J Microelectronics Reliability, vol. 51, pp. 1365-1371, 2011.
  24. S. Maheshwaram, S. Manhas, G. Kaushal, B. Anand, and N. Singh, "Vertical silicon nanowire gate-all-around field effect transistor based nanoscale CMOS," IEEE Electron Device Letters, vol. 32, pp. 1011-1013, 2011.
  25. N. Singh, K. D. Buddharaju, S. Manhas, A. Agarwal, S. C. Rustagi, G. Lo, N. Balasubramanian, and D.-L. Kwong, "Si, SiGe nanowire devices by top–down technology and their applications," IEEE Transactions on Electron Devices, vol. 55, pp. 3107-3118, 2008.
  26. M. M. De Souza, S. Manhas, D. C. Sekhar, A. Oates, and P. Chaparala, "Influence of mobility model on extraction of stress dependent source–drain series resistance," Microelectronics Reliability, vol. 44, pp. 25-32, 2004.
  27. G. Cao, S. Manhas, E. S. Narayanan, M. De Souza, and D. Hinchley, "Comparative study of drift region designs in RF LDMOSFETs," IEEE Transactions on Electron Devices, vol. 51, pp. 1296-1303, 2004.
  28. S. Manhas, D. C. Sehkar, A. Oates, and M. M. De Souza, "Characterisation of series resistance degradation through charge pumping technique," Microelectronics Reliability, vol. 43, pp. 617-624, 2003.
  29. S. Manhas, M. M. De Souza, and A. S. Oates, "Quantifying the nature of hot carrier degradation in the spacer region of LDD nMOSFETs,"  IEEE transactions on device materials reliability, vol. 1, pp. 134-143, 2001.
  30. M. M. De Souza, J. Wang, S. Manhas, E. S. Narayanan, and A. Oates, "A comparison of early stage hot carrier degradation behaviour in 5 and 3 V sub-micron low doped drain metal oxide semiconductor field effect transistors," Microelectronics Reliability, vol. 41, pp. 169-177, 2001.
  31. S. Manhas, D. C. Sekhar, A. Oates, and M. De Souza, "Nature of hot carrier damage in spacer oxide of LDD n-MOSFETs," in Microelectronics, 2002. MIEL 2002. 23rd International Conference on, 2002, pp. 735-739.
  32. S. Manhas, M. De Souza, A. Oates, and Y. Chen, "Impact of oxide degradation on universal mobility behaviour of n-MOS inversion layers," in Physical and Failure Analysis of Integrated Circuits, 2002. IPFA 2002. Proceedings of the 9th International Symposium on the, 2002, pp. 227-231.
  33. S. Manhas, M. De Souza, A. Gates, S. Chetlur, and E. S. Narayanan, "Early stage hot carrier degradation of state-of-the-art LDD N-MOSFETs," in Reliability Physics Symposium, 2000. Proceedings. 38th Annual 2000 IEEE International, 2000, pp. 108-111.
  34. S. Maheshwaram, O. Prakash, M. Sharma, A. Bulusu, and S. Manhas, "Vertical Nanowire FET Based Standard Cell Design Employing Verilog-A Compact Model for Higher Performance," in International Symposium on VLSI Design and Test, 2017, pp. 239-248.
  35. O. Prakash, S. Maheshwaram, M. Sharma, A. Bulusu, A. Saxena, and S. Manhas, "A unified Verilog-A compact model for lateral Si nanowire (NW) FET incorporating parasitics for circuit simulation," in 2016 20th International Symposium on VLSI Design and Test (VDAT), 2016, pp. 1-6.
  36. S. Gautam, S. Maheshwaram, S. Manhas, A. Kumar, S. Sherman, and S. H. Jo, "Reduction of GIDL Using Dual Work-Function Metal Gate in DRAM," in Memory Workshop (IMW), 2016 IEEE 8th International, 2016, pp. 1-4.
  37. M. Sharma, S. Maheshwaram, O. Prakash, A. Bulusu, A. Saxena, and S. Manhas, "Compact model for vertical silicon nanowire based device simulation and circuit design," in SoC Design Conference (ISOCC), 2015 International, 2015, pp. 107-108.
  38. S. Maheshwaram, S. Manhas, and B. Anand, "Vertical nanowire transistor-based CMOS: VTC analysis," in Emerging Electronics (ICEE), 2014 IEEE 2nd International Conference on, 2014, pp. 1-4.
  39. S. Maheshwaram, S. Manhas, G. Kaushal, and B. Anand, "Vertical nanowire MOSFET parasitic resistance modeling," in Electron Devices and Solid-State Circuits (EDSSC), 2013 IEEE International Conference of, 2013, pp. 1-2.
  40. G. Kaushal, S. Maheshwaram, S. Dasgupta, and S. Manhas, "Drive matching issues in multi gate CMOS inverter," in Signal Processing and Communication (ICSC), 2013 International Conference on, 2013, pp. 349-354.
  41. H. Zhao, S. Rustagi, N. Singh, F.-J. Ma, G. Samudra, K. Budhaaraju, S. Manhas, C. Tung, G. Lo, and G. Baccarani, "Sub-femto-farad capacitance-voltage characteristics of single channel gate-all-around nano wire transistors for electrical characterization of carrier transport," in Electron Devices Meeting, 2008. IEDM 2008. IEEE International, 2008, pp. 1-4.
  42. S. K. Manhas, M Chen, K D Buddharaju, H Y Li, R Murthy, S Balakumar, N singh, G Q Lo and D L Kwong, “Copper Plug Barrier Process Optimization for Reliable Transistor Performance,” International Symp on Solid State Circuits and Materials (SSDM 2008), 23 - 26 Sep, p. 390, 2008, Japan
  43. A. Basak, S. Manhas, G. Kapil, S. Dasgupta, and N. Jain, "A Simulation Study of the Effect of Platinum Contact on CNT Based Gas Sensors Using Self-Consistent Field with NEGF Method," in Int. Conf. on Semiconductor Processes and Devices (SISPAD), USA, 2012.
  44. S. Maheshwaram, G. Kaushal, and S. Manhas, "A high performance vertical Si nanowire CMOS for ultra high density circuits," in Circuits and Systems (APCCAS), 2010 IEEE Asia Pacific Conference on, 2010, pp. 1219-1222.

Patents

  1. S K Manhas, S Nema, Dr A Bulusu, “A method of fabricating dual/asymmetric dielectric constant (dual-K) spacers in MOSFET,” No R20161028626, 2012 (filed), IIT Roorkee.
  2. S. K. Manhas, G. Kaushal, Anand Bulusu, “A Design Methodology using Extension Length (LEXT) Sizing in Nanowire CMOS Logic,” approved for filing by IP cell IIT Roorkee.
  3. Arvind KUMAR, Mahendra PAKALA, and Satendra Kumar GAUTAM, Sanjeev MANHAS, “DRAM AND METHOD OF MAKING,” No. 44015725US01, 2018 (Filed).
  4. Sandeep Chauhan, S K Manhas, Manish Joglekar, “CMOS Compatible Micro-machined Piezoelectric Energy Harvester.” Appl no 201911020224, 2019 (Filed).