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Brajesh Kumar Kaushik
Brajesh Kumar Kaushik Associate Professor bkk23fec[at]iitr.ac.in +91-1332-285662 Website
Areas of Interest
  • Nanotechnology Design, Nanoscale Interconnects and Devices; CNT Based Applications; Organic Electronics; Spintronics
Professional Background
FromToDesignationOrganisation
19971998Research and Development EngineerVinytics Peripherals Pvt Ltd Delhi
19982003LecturerG.B.Pant Engineering College Pauri Garhwal
20032005Senior LecturerG.B.Pant Engineering College Pauri Garhwal
20052006Assistant ProfessorG.B.Pant Engineering College Pauri Garhwal
20062009Associate ProfessorG.B.Pant Engineering College Pauri Garhwal
20092014Assistant ProfessorIndian Institute of Technology-Roorkee
2014ContinuingAssociate ProfessorIndian Institute of Technology-Roorkee
Honors and Awards
AwardInstituteYear
EditorIEEE Transactions on Electron Devices2018
Distinguished Lecturer (DL)IEEE Electron Devices Society2017
Associate EditorIET Circuits, Devices & Systems (IET-CDS)2017
Visiting LecturerSPIE Society2019
EditorMicroelectronics Journal, Elsevier2014
Senior MemberIEEE2013
Editorial Advisory BoardJournal of Engineering, Design and Technology (JEDT), Emerald Group Publishing Limited, UK2012
Editor-in-ChiefInternational Journal of VLSI Design and Communication System (VLSICS), AIRCC Publishing Corporation2010
Editorial Board MemberCircuit World, Emerald Publishing2018
IETE – GOWRI MEMORIAL AWARD for “Design of LMS Adaptive Radar Detector"Institute of Electronics and Telecommunication Engineers2017
Shastri Scholar Travel Subsidy Grant (SSTSG)Shastri Indo Canadian Institute (SICI)2017-18
Shastri Research Grant (SRG) in Collaboration with McGill University, MontrealShastri Indo Canadian Institute (SICI)2017-18
Educational Details
DegreeSubjectUniversityYear
PhDDelay and Crosstalk Analysis of CMOS Driven VLSI InterconnectsIndian Institute of Technology Roorkee2007
Sponsored Research Projects
TopicFunding AgencyYear
Strengthening of Digital Signal Processing LaboratoryAICTE (MODROBS)2001
Modeling and Simulation of Novel Structures of OTFTs and OLEDs and their Application in VLSI CircuitFIG-IITR2011
Study of Heat Shimmer Removal Techniques for Long Range Imaging SystemsDRDO2013
Development of Restoration Techniques for Weather Degraded ImagesDRDO2015
Development and Real-Time Implementation of Filters to Remove Noise and Blur EffectDRDO2016
Thermal Imager and Its Calibrator for Bad Weather and Night VisionSMILE, IITR2017
Analysis and Performance Enhancement of Graphene Plasmonic AntennasSAC, ISRO2018
Brain Computer Interface for Neuro and Cognitive ResearchSMILE, IIT Roorkee2018
Development of Low Cost Indigenous Earthquake Early Warning SystemIMPRINT-2, SERB, DST2018
Modeling and Design of All-Optical Switching Devices for DWDM System and Sensors for Health MonitoriSERB, DST2018
Design and Analysis of Spintronics Based Devices to SystemsShastri Research Grant (SRG)- Shastri Indo Canadian Institute (SICI)2018
Transient Absorption, Time Resolved Fluorescence and Sum Frequency Generation SpectroscopySMILE, IIT Roorkee2019
Spintronics Based In-Memory Computing for Neuromorphic ApplicationsSPARC, MHRD2019
Massive Parallel Interconnect Architectures for Vision SoC: Exploiting Graphene Nanophotonic Tech.DSD-DAAD2019
Spin Orbit Coupling based IntelligencE TechnologY (SOCIETY) National Research Foundation, PMO, Singapore2019
PHDs Supervised
TopicScholar NameStatus of PHDRegistration Year
Effects of Process Variation on the Performance Parameter of VLSI InterconnectsK. G. VermaA2008
Organic Thin Film Transistor Device Modeling, Circuit Co-Design and Performance AnalysisBrijesh KumarA2009
Modeling, Performance Analysis and Testing of InterconnectsDevendra Kumar SharmaA2009
Performance Analysis of Graphene Based Interconnects and Through Silicon ViasManoj Kumar MajumderA2010
Dual-k Spacer Engineered Devices for High Performance Digital Circuit/SRAM Applications Pankaj Kumar PalA2010
Modeling of Crosstalk Effects in CMOS Gate Driven On-chip Interconnects Using FDTD TechniqueRamesh Kumar VobulapuramA2011
Design of Spin Transfer Torque Based Memory and LogicShivam VermaA2013
Video Processing and Analytics for Smart Camera based on Reconfigurable ArchitectureManoj PurohitO2014
VLSI Implementation of Video Processing Techniques for Electro-optic Surveillance SystemManvendra SinghO2014
Signal Processing Architecture for Advanced Infrared (IR) DetectorsSudhir KhareO2014
Design and Modeling of III-V Hetero-Junction Tunnel FETs and their Circuit ApplicationsPrabhat Kumar DubeyO2014
Design of Nano-Scale Spin Torque Memory and LogicSanjay PrajapatiO2015
Spintronics Based Computing ArchitecturesKulkarni Anant AravindO2015
Efficient Electro-Optic Modulator Design for On-Chip Optical InterconnectsSwati JoshiO2015
Design of High Density-Low Power Memory DevicesSonal ShreyaO2015
Performance Modeling and Analysis of Graphene-Based On-Chip VLSI InterconnectsAmit KumarO2015
Performance Analysis of Emerging Non-Volatile Memory Devices and CircuitsVikas NehraO2016
Visibility Enhancement of Weather Degraded Images and VideosRahul KumarO2016
VLSI Architecture for High Speed Image ProcessingGyanendraO2016
Visits to outside institutions
Institute VisitedPurpose of VisitDate
Princeton University, NJ 08544, USAResearch Interaction24-3-2012
Massachusetts Institute of Technology, Cambridge, Massachusetts, USAResearch Visit14-6-2014
Princeton University, NJ 08544, USAResearch Interaction6-6-2014
AIRCC, Dubai, UAEInvited Talk in Conference24-4-2015
Monash University, Kuala Lumpur, MalaysiaInvited Talk on Research Activities29-5-2015
Nanyang Technological University, SingaporeResearch Collaboration3-6-2015
Chiang Mai University, Chiang Mai, ThailandResearch Talk17-6-2015
AIRCC, Dubai, UAEInvited Talk in Conference23-1-2016
Manipal University, Dubai, UAETalk on Research Activities24-1-2016
AIRCC, Dubai, UAEInvited Talk in Conference23-4-2016
Manipal University, Dubai, UAEResearch Interaction24-4-2016
AIRCC, Dubai, UAEKeynote Address in AIRCC Conference24 -9-2016
BITS Pilani Dubai CampusInvited Talk and Research Interaction25-9-2016
The University of Nottingham, Kuala Lumpur, MalaysiaResearch Evaluation and Interaction9-1-2017
AIRCC, Dubai, UAEKeynote Address and General Chair in Conference28-1-2017
AIRCC Conference, Dubai, UAEKeynote address on "Spintronics-Perspectives and Challenges"29-04-2017
Technical University of Dortmund, Germany TU9-IIT Exchange of Faculty (Bilateral Exchange of Academics) under DAAD Fellowship from 1 June 2017 to 31 July 2017Two Months
Karlsruhe Institute of Technology, Karlsruhe, GermanyInvited Talk and Research Collaboration 14-07-2017
IMEC, Leuven, BelgiumIEEE EDS Distinguished Lecture and Research Collaboration17-07-2017
AIRCC Conference, Dubai, UAEKeynote Address and General Chair in Conference25-11-17
Liaocheng University, Shandong Province, ChinaResearch Collaboration23-29/5/18
Nanyang Technological University, SingaporeResearch Interaction and Strategic Collaboration26-28/8/17
McGill University, Montreal, Canada Joint Research with McGill University, Montreal, Canada under Indo Canadian Shastri Research Grant (SRG) 10-25/9/18
Liaocheng University (LCU), Liaocheng, Shandong Province, ChinaJoint Research in the area of Fibre based Biosensors (1 month)16-12-18
Fert Beijing Institute, School of Microelectronics, Beihang University, Beijing, ChinaInvited Lecture on "Spintronics based Design" and Research Collaboration31-12-2018
Chengdu University of Technology, Chengdu, ChinaInvited Lecture on "Real Time Image Processing"12-01-2019
Courses or Conferences Organised
Conference NameSponsored ByDate
Micro and Nano Electro-Mechanical Systems (MEMS & NEMS) (23 to 27 June, 2014) - CoordinatorAICTE23-27 June
14th IEEE India Council International Conference (INDICON 2017), 15-17 Dec, 2017IEEE India Council and IEEE UP Section15-17 Dec
Image Processing using VLSI Architectures (6-10 July, 2015) - CoordinatorAICTE6-10 July
Introduction to Spintronics (18 to 22, Dec-2017) - CoordinatorMHRD under GIAN with Prof. Supriyo Bandyopadhyay, Virginia Commonwealth University, Richmond, USA18-22 Dec
Logic Design Under Paradigm of Rebooting Computing (25 to 29, Dec-2017) - CoordinatorMHRD under GIAN with Prof. Himanshu Thapliyal, University of Kentucky, Lexington, KY, USA25-29 Dec
IoT - Technology, Applications and Implementation Perspectives (4 to 8 April, 2018)- CoordinatorE&ICT Academy with Dr. P. K. Meher, NTU-Singapore4-8 April
Image Processing using VLSI Architectures (26-30 Mar, 2019)-CoordinatorE&ICT Academy26-30, Mar
Artificial Intelligence-Devices to Systems (28 Aug- 01 Sep, 2019) - CoordinatorE&ICT Academy28/8 - 1/9
Special Lectures Delivered
TitlePlaceDate
IEEE EDS Distinguished Lecture on “Spintronics-Perspectives and Challenges”Australian National University, Canberra, Australia.13-04-2017
IEEE EDS Distinguished Lecture on "Graphene based Interconnect Modelling"Monash University Clayton, Victoria Australia.17-04-2017
IEEE EDS Distinguished Lecture on “Spintronics-Perspectives and Challenges”IMEP-LAHC, Grenoble-INP, France13-07-2017
Invited Lecture on "Spintronics- Memories and Logics"Karlsruhe Institute of Technology, Karlsruhe, Germany14-07-2017
IEEE EDS Distinguished Lecture on “Spintronics-Perspectives and Challenges”IMEC, Leuven, Belgium17-07-2017
Invited lecture on "Modelling and Application of FinFET"Birla Institute of Technology & Science, Pilani-Dubai Campus26-11-2017
Invited Lecture on "Paradigm Shift from Electrical to Optical Domain"Liaocheng University, Shandong Province, China28-5-2017
IEEE EDS Distinguished Lecture on "Modeling and Applications of FinFET"Southeast University, ED Nanjing Chapter, China31-5-2018
IEEE EDS Distinguished Lecture on “Spintronics-Perspectives and Challenges”IEEE Singapore EDS Chapter, Nanyang Technological University, Singapore29-8-2018
Spintronics- Memories and LogicsMcGill University, Montreal, Canada14-9-2018
Graphene based Interconnect ModellingIEEE Ottawa Section, at Carleton University, Ottawa, Ontario, Canada21-9-2018
Modeling and Applications of FinFETUniversity of Electronic Science and Technology of China, ED Chengdu Chapter, Sichuan, China11-01-2019
Graphene based Interconnect ModelingInstitute of Engineering, IEEE EDS Nepal Chapter, Kathmandu13-01-2019
IEEE EDS Distinguished Lecture on "Spintronics-Perspectives and Challenges"Texas Instruments Conference Centre, Santa Clara, CA, USA5-3-2019
Spintronics based Logics and MemoriesThe University of The West Indies, St. Augustine, Trinidad and Tobago12-3-2019
National International Collaboration
TopicOrganisationLevel
Design and Analysis of Spintronics Based Devices to SystemsMcGill University, CanadaRP
Spin Orbit Coupling based IntelligencE TechnologY (SOCIETY)Nanyang Technological University, SingaporeRP
Massive Parallel Interconnect architectures for Vision Systems-on-Chip: Exploiting Graphene Nanophotonic TechnologiesUniversity of Bremen, GermanyRP
Spintronics Based In-Memory Computing for Neuromorphic ApplicationsPurdue University, USA and Intel Inc., USARP
Design and Modeling of Tunnel FET IMEC, BelgiumRP
2D material based tunneling field-effect transistor for biomedical sensing applicationsUniversity of Glasgow, UKRP
Skymion Based Neuromorphic ComputingNanyang Technological University, SingaporePHD
Performance Analysis of Emerging Non-Volatile Memory Devices and CircuitsUniversity of NottinghamPHD
Books Authored

BOOK CHAPTERS

Chapter Title: Testing of CMOS driven VLSI Interconnects

Authors: Devendra Kumar Sharma, Brajesh Kumar Kaushik and R. K. Sharma

Publication Title: Transmission Lines: Theory, Types and Applications

Publisher: Nova Science Publishers, Inc., New York, USA

ISBN: 978-1-61761-300-5

 

Chapter Title: VLSI Interconnects and their Delay Performance.

Authors: Brajesh Kumar Kaushik, R.P. Agarwal, R. C. Joshi and Sankar Sarkar.

Publication Title: VLSI and Computer Architecture

Publisher: Nova Science Publishers, Inc., New York, USA

ISBN: 978-1-60692-075-6

 

Chapter Title: Roadmap to Radio Frequency Identification and Library Implementation: A Review.

Authors: Viplove Goel, Anil Chauhan, Shailesh Goswami, Rohit Bankoti and B.K. Kaushik.

Publication Title: Radio Frequency Identification

Publisher: Nova Science Publishers, Inc., New York, USA

ISBN: 978-1-61122-416-0

 

Chapter Title: Fabrication and Modelling of Copper and Carbon Nanotube based Through-Silicon Via.

Authors: Brajesh Kumar Kaushik, Manoj Kumar Majumder and Archana Kumari

Publication Title: Design of 3D Integrated Circuits and Systems (Devices, Circuits, and Systems)

Publisher: CRC Press, Taylor & Francis.

ISBN-13: 978-1466589407

 

Chapter Title: Paradigm Shift of On-Chip Interconnects from Electrical to Optical

Authors: Swati Joshi, Amit Kumar, Brajesh Kumar Kaushik

Publication Title: Noise Coupling in System-on-Chip (Devices, Circuits, and Systems)

Publisher: CRC Press, Taylor & Francis.

ISBN-13: 9781498796774 

 

BOOKS AUTHORED

Book Title: Analog Integrated Circuits

Authors: B. K. Kaushik and Deepak Garg

Publisher: Pragati –Prakashan, Meerut

 

Book Title: Electronics Engineering

Authors: B. K. Kaushik, Abhishek Yadav and Poonam Yadav

Publisher: University Science Press, Delhi

ISBN: 978-93-80386-43-0

 

Book Title: Carbon Nanotube Based VLSI Interconnects-Analysis and Design

Authors: Brajesh Kumar Kaushik and Manoj Kumar Majumder

Publisher: Springer, Heidelberg Germany

 

Book Title: Microelectromechanical Systems (MEMS)

Authors: Bhattacharya Dilip Kumar and Brajesh Kumar Kaushik

ISBN: 9788131525883 

Publisher: Cengage Learning

 

Book Title: Crosstalk in Modern On-Chip Interconnects- A FDTD Approach

Authors: B.K.Kaushik, V. Ramesh Kumar and Amalendu Patnaik

Publisher: Springer, Heidelberg Germany

 

Book Title: Organic Thin-Film Transistor Applications: Materials to Circuits

Authors: Brajesh Kumar Kaushik, Brijesh Kumar, Sanjay Prajapati, Poornima Mittal

Publisher: CRC Press, Taylor & Francis Group, UK/USA

 

Book Title: Through Silicon Vias: Materials, Models, Design, and Performance

Authors: Brajesh Kumar Kaushik, Vobulapuram Ramesh Kumar, Manoj Kumar Majumder, Arsalan Alam

Publisher: CRC Press, Taylor & Francis Group, UK/USA

 

Book Title: Spin Transfer Torque Based Devices, Circuits, and Memory

Authors: Brajesh Kumar Kaushik and Shivam Verma

Publisher: Artech House, Boston (USA) and London (UK)

 

Book Title: Spacer Engineered FinFET Architectures: High-Performance Digital Circuit Applications

Authors: Brajesh Kumar Kaushik, Sudeb Dasgupta, Pankaj Kumar Pal

Publisher: CRC Press, Taylor & Francis Group, UK/USA

 

Book Title: Next Generation Spin Torque Memories

Authors: Brajesh Kumar Kaushik, Shivam Verma, Kulkarni Anant Aravind, Sanjay Prajapati 

Publisher: Springer, Heidelberg Germany

 

Book Title: Nanoelectronics-Devices, Circuits and Systems

Editor: Brajesh Kumar Kaushik

Publisher: Micro and Nano Technologies, Elsevier

 

Book Title: Nanoscale Devices: Physics, Modeling, and Their Application

Editor: Brajesh Kumar Kaushik

Publisher: CRC Press, Taylor & Francis Group, UK/USA

 

EDITOR OF CONFERENCE PROCEEDINGS

TitleAdvances in Computer Science and Information Technology

Authors: Natarajan Meghanathan, Brajesh Kumar Kaushik and Dhinaharan Nagamalai

Publisher: Springer, Heidelberg Germany

 

TitleAdvances in Networks and Communications

Authors: Natarajan Meghanathan, Brajesh Kumar Kaushik and Dhinaharan Nagamalai

Publisher: Springer, Heidelberg Germany

 

TitleAdvanced Computing

Authors: Natarajan Meghanathan, Brajesh Kumar Kaushik and Dhinaharan Nagamalai

Publisher: Springer, Heidelberg Germany

 

Title:  VLSI Design and Test

AuthorsBrajesh Kumar Kaushik, Sudeb Dasgupta, Virendra Singh 

Publisher: Springer, Heidelberg Germany

Refereed Journal Papers

Year - 2019

  • Piyush Tankwal, Vikas Nehra, Sanjay Prajapati, Brajesh Kumar Kaushik, “Performance Analysis of Differential Spin Hall Effect (DSHE)-MRAM Based Logic Gates”, Circuit World, 2019 (Article in Press).
  • Lokendra Singh, Zhu Guo, Ragini Singh, Bingyuan Zhang, Wenjun Wang, Brajesh Kumar Kaushik, and Santosh Kumar, "Gold nanoparticles and Uricase Functionalized Tapered Fiber Sensor for Uric Acid Detection", IEEE Sensors Journal, 2019 (Article in Press).
  • Niteshkumar Agrawal, Bingyuan Zhang, Chinmoy Saha, Chandrakanta Kumar, Brajesh Kumar Kaushik and Santosh Kumar, "Development of Dopamine Sensor using Silver Nanoparticles and PEG- Functionalized Tapered Optical Fiber Structure",  IEEE Transactions on Biomedical Engineering, 2019 (Article in Press).
  • Vikas Nehra, Sanjay Prajapati, Piyush Tankwal, Zeljko Zilic, T. Nandha Kumar and Brajesh Kumar Kaushik, "Energy Efficient Differential Spin Hall MRAM based 4-2 Magnetic Compressor", IEEE Transactions on Magnetics, 2019 (Article in Press).
  • Anant Kulkarni and Brajesh Kumar Kaushik, "Spin-torque-based Quantum Fourier Transform", IEEE Transactions on Magnetics, 2019 (Article in Press).
  • Anant Kulkarni, Namita Bindal, and Brajesh Kumar Kaushik, "Quantum Computing Circuits Based on Spin-Torque Qubit Architecture", IEEE Nanotechnology Magazine10.1109/MNANO.2019.2927782 (Article in Press)
  • Rahul Kumar, Brajesh Kumar Kaushik, and R. Balasubramanian, "Multispectral Transmission Map Fusion Method and Architecture for Image Dehazing," IEEE Transactions on Very Large Scale Intergration (VLSI) Systems, 2019 (Article in Press)
  • Swati Joshi, P.K.Dubey, and Brajesh Kumar Kaushik, "A Transition Metal Dichalcogenide Tunnel FET Based Waveguide-Integrated Photodetector Using Ge for Near-Infrared Detection" IEEE Sensors Journal, 2019 (Article in Press).
  • Sonal Shreya and Brajesh Kumar Kaushik, “Differential Spin Hall Effect based Nonvolatile Static Random Access Memory for Energy Efficient and Fast Data Restoration Application” IEEE Transactions on Magnetics, 2019 (Article in Press).
  • Chanderkanta, Nan-Kuang Chen, Brajesh Kumar Kaushik and Santosh Kumar, “Implementation of reversible Peres gate using electro-optic effect inside lithium-niobate based Mach-Zehnder interferometers,” Optics & Laser Technology, vol. 117, pp. 28-37, Sep 2019.
  • Santosh Kumar, Ragini Singh, Brajesh Kumar Kaushik, Nan-Kuang Chen, Qing Shan Yang, Xia Zhang, "LSPR based cholesterol biosensor using hollow core fiber structure,” IEEE Sensors Journal, 2019 (Article in Press), DOI: 10.1109/JSEN.2019.2916818.
  • P. K. Dubey and Brajesh Kumar Kaushik, “A charge plasma-based monolayer transition metal dichalcogenide tunnel FET,” IEEE Transactions on Electron Devices, 2019 (Article in Press), DOI: 10.1109/TED.2019.2909182.
  • P. K. Dubey, Brajesh Kumar Kaushik, and E. Simoen, “Analytical modeling and device design optimization of epitaxial layer based III-V tunnel FET,” IET Circuits, Devices & Systems, 2019 (Article in Press), DOI:  10.1049/iet-cds.2018.5169.
  • Chanderkanta Chauhan, Brajesh Kumar Kaushik and Santosh Kumar, “Design of optical reversible hybrid adder-subtractor device using Mach-Zehnder interferometers for WDM applications,” Journal of Optical Communications, 2019 (Article in Press), DOI:10.1515/joc-2019-0031
  • Lokendra Singh, Santosh Kumar and Brajesh Kumar Kaushik, “All-optical switching device using plasmonic Mach-Zehnder interferometer structure,” Journal of Optical Communications, 2019 (Article in Press), DOI: 10.1515/joc-2018-0215.
  • Santosh Kumar, Brajesh Kumar Kaushik, Ragini Singh, Nan-Kuang Chen, Qing Shan Yang, Xia Zhang, Wenjun Wang, Bingyuan Zhang, “LSPR based cholesterol biosensor using tapered optical fiber structure,” Biomedical Optics Express, vol. 10, no. 5, pp. 2150-2160, May 2019 (2017-Impact Factor: 3.482)
  • S. Dash, A. Patnaik and Brajesh Kumar Kaushik, “Performance enhancement of graphene plasmonic nanoantennas for THz communication,” IET Microwaves, Antennas & Propagation, vol. 13, no. 1, pp. 71-75, 2019.
  • Sudhir Khare, Manvendra Singh, and Brajesh Kumar Kaushik, “Real time non uniformity correction algorithm and implementation in reconfigurable architecture for infrared imaging systems”, Defence Science Journal, vol. 69, no. 2, pp. 179-184, Mar. 2019.
  • Sanjay Prajapati and Brajesh Kumar Kaushik, "Area and energy efficient series multilevel cell STT-MRAMs for optimized read–write operations," IEEE Transactions on Magnetics, vol. 55, no. 1, pp. 1-10, Jan. 2019.

Year - 2018

  • Amit Kumar, V. R. Kumar and Brajesh Kumar Kaushik, “Transient Analysis of Crosstalk Induced Effects in Mixed CNT Bundle Interconnects Using FDTD Technique”, IEEE Transactions on Electromagnetic Compatibility, 2018 (Article in Press). DOI: 10.1109/TEMC.2018.2872899.
  • S. Prajapati, S. Verma, A. A. Kulkarni, and Brajesh Kumar Kaushik, “Modeling of magnetic tunnel junction for multilevel STT-MRAM cell,” IEEE Transactions on Nanotechnology, 2018 (Article in Press) DOI: 10.1109/TNANO.2018.2875491.
  • Tanu Goyal, Manoj Kumar Majumder and Brajesh Kumar Kaushik, “Modeling and fabrication aspects of Cu- and carbon nanotube-based through-silicon vias”, IETE Journal of Research, 2018 (Article in Press)  DOI: 10.1080/03772063.2018.1553638.
  • A. Kulkarni, S. Prajapati, and Brajesh Kumar Kaushik, “Transmission coefficient matrix modeling of spin-torque based n-qubit architecture,” IEEE Transactions on VLSI, vol. 26, no. 8, pp. 1461-1470, Aug 2018.
  • A. Kulkarni, S. Prajapati, S. Verma, and Brajesh Kumar Kaushik, “Optimal Boolean logic quantum circuits decomposition for spin-torque based n-qubit architecture,” IEEE Transactions on Magnetics, vol. 54, no. 10, Oct. 2018.
  • S. Prajapati and Brajesh Kumar Kaushik, “Parallel multilevel cell STT-MRAMs for optimized area energy and read–write operations,” IEEE Transactions on Magnetics, vol. 54, no. 6, Jun. 2018.
  • Sudhir Khare, Manvendra Singh, and Brajesh Kumar Kaushik, “Range performance modelling of thermal imaging system based on single parameter characterised by ambient temperature and relative humidity”, Defence Science Journal, vol. 68, no. 5, pp. 480-486, Sep. 2018.
  • P. Goyal, S. Gupta, G. Kaur, and Brajesh Kumar Kaushik, “Performance analysis of VCSEL using finite difference time domain method,” Optik-International Journal for Light and Electron Optics, vol. 156, pp. 505-5013, Mar. 2018.
  • B. Vandana, B. S. Patro, J. K. Das, Brajesh Kumar Kaushik and S. K. Mohapatra, “Inverted ‘T’ junctionless FinFET (ITJL FinFET): Performance estimation through device geometry variation,” ECS Journal of Solid State Science and Technology, vol. 7, no. 4, pp. Q52-Q59, 2018.
  • M. K. Rai, S. Arora, and Brajesh Kumar Kaushik, “Temperature‐dependent modeling and performance analysis of coupled MLGNR interconnects”, International Journal of Circuit Theory and Applications, vol.46, no. 2, pp. 299-312, 2018.

Year - 2017

  • R. Mehra, V. Kumar, A. Islam, and Brajesh Kumar Kaushik, “Variation-aware widely tunable nanoscale design of CMOS active inductor-based RF bandpass filter,” International Journal of Circuit Theory and Applications, Wiley,  vol 45, no. 12, pp. 2181-2200, Dec 2017.
  • P. K. Dubey, and Brajesh Kumar Kaushik, “T-shaped III-V heterojunction tunneling field-effect transistor,” IEEE Transactions on Electron Devices, vol. 64, no. 8, Aug. 2017.
  • Rahul Kumar, Manoj Purohit, Deepa Saini, and Brajesh Kumar Kaushik, “Air turbulence mitigation techniques for long-range terrestrial surveillance,” IETE Technical Review Journal, vol. 34, no. 4, pp. 416-430, Jul. 2017.
  • M. K. Rai, H. Garg, and Brajesh Kumar Kaushik, “Temperature-dependent modeling and crosstalk analysis in mixed carbon nanotube bundle interconnects,” Journal of Electronic Materials, Springer, vol. 46, no. 8, pp. 5324–5337, May 2017.
  • R. Bajaj, H. K. Mishra, P. Goyal, G. Kaur, and Brajesh Kumar Kaushik, “Design of oxide-confined and temperature stable long wavelength vertical cavity surface emitting laser for optical interconnects,” Optik-International Journal for Light and Electron Optics, Elsevier, vol. 131, pp. 506-514, Feb. 2017.

Year - 2016

  • S. Dahiya, S. Kumar, and Brajesh Kumar Kaushik, “Modeling and optimization of single-mode vertical cavity surface emitting lasers,” Journal of Nanophotonics, International Society for Optics and Photonics (SPIE), vol. 10, no. 4, pp. 046008-046008, Oct. 2016.
  • S. Dahiya, S. Kumar, and Brajesh Kumar Kaushik, “Hybrid plasmonic waveguide with centimeter-scale propagation length for nanoscale optical confinement,” Applied Optics, Optical Society of America, vol. 55, no. 36, pp. 10341-10346, Dec. 2016. 
  • Shivam Verma, Anant Aravind Kulkarni, and Brajesh Kumar Kaushik, “Spintronics based devices to circuits: perspectives and challenges,” IEEE Nanotechnology Magazine, vol.10, no. 4, pp. 2-19, December 2016.  DOI: 10.1109/MNANO.2016.2606683
  • A. Mandal, R. Mishra, B. K. Kaushik and N. Z. Rizvi, “Design of LMS adaptive radar detector for non-homogeneous interferences,” IETE Technical Review Journal, vol. 33, no. 3, pp. 269-279, Oct. 2016. (Received IETE-GOWRI MEMORIAL AWARD-2017)
  • Shivam Verma, Pankaj Kumar Pal, Sanjay Mahawar and Brajesh Kumar Kaushik, "Performance enhancement of STT MRAM using asymmetric- k sidewall-spacer NMOS" IEEE Transactions on Electron Devices, vol. 63, no. 7, pp. 2771 - 2776, July 2016.  
  • M. K. Rai, A. K. Chatterjee, S. Sarkar, and B. K. Kaushik, “Performance analysis of multilayer graphene nanoribbon (MLGNR) interconnects,” Journal of Computational Electronics, Springer, vol. 15, no. 2, pp. 358-366, June 2016.
  • Mayank Kumar Rai, Brajesh Kumar Kaushik, S. Sarkar, "Thermally aware performance analysis of single-walled carbon nanotube bundle as VLSI interconnects," Journal of Computational Electronics, Springer, vol. 15, no. 2, pp 407-419, June 2016.
  • Shivam Verma, and Brajesh Kumar Kaushik, “Low power high Density STT MRAMs on 3D vertical silicon nano-wire platform,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 4, pp. 1371-1376, April 2016.

 ​Year - 2015 

  • V. Ramesh Kumar, A. Alam, Brajesh Kumar Kaushik, and A. Patnaik, “An unconditionally stable FDTD model for crosstalk analysis of VLSI interconnects,” IEEE Transactions on Components, Packaging, and Manufacturing Technology, vol. 5, no. 12, pp. 1810-1817, Dec. 2015.
  • V. Ramesh Kumar, Brajesh Kumar Kaushik, and  A. Patnaik, “Improved crosstalk noise modeling of MWCNT interconnects using FDTD technique,” Microelectronics JournalElsevier, vol. 46, no. 12, pp. 1263-1268, Dec. 2015.
  • J. K. Thind, M. Kumar, and Brajesh Kumar Kaushik, “Electrical tuning of optical delay in graphene-based photonic crystal waveguide,” IEEE Journal of Quantum Electronics, vol. 51, no. 10, Oct. 2015.
  • A. Mandal, R. Mishra, Brajesh Kumar Kaushik, and N. J. Rizvi, “Design of LMS adaptive radar detector for non-homogeneous interferences,” IETE Technical Review, Oct. 2015, DOI: 10.1080/02564602.2015.1093436.
  • M. Joshi, D. S. Chauhan, and Brajesh Kumar Kaushik, “A new high speed full adder cell,” World Applied Sciences Journal, vol. 33, no. 4, pp. 599-603, 2015.
  • Manoj Kumar Majumder, Pankaj Kumar Das, Vobulapuram Ramesh Kumar, and Brajesh Kumar Kaushik“Crosstalk induced delay analysis of randomly distributed mixed CNT bundle interconnect,” Journal of Circuits, Systems and Computers, vol. 24, no. 10, Aug. 2015.
  • Shivam Verma, M. Satyanarayana Murthy, and Brajesh Kumar Kaushik, “All Spin Logic (ASL): A Micromagnetic Perspective,” IEEE Transactions on Magnetics, vol. 51, no. 10, 2015, DOI: 10.1109/TMAG.2015.244581.
  • S. K. Verma and Brajesh Kumar Kaushik, “Bus encoder design for crosstalk and power reduction in RLC modelled VLSI interconnects,” Journal of Engineering, Design and Technology, vol. 13, no. 3, pp. 486–498, Jul. 2015.
  • T. Goyal, M. K. Majumder, and Brajesh Kumar Kaushik, “Propagation delay and power dissipation for different aspect ratio of single-walled carbon nanotube bundled TSV,” Journal of Semiconductor, vol. 36, no. 6, p. 065001, Jun. 2015.
  • Y. S. Duksh, Brajesh Kumar Kaushik, and R. P. Agarwal, “FDTD technique based crosstalk analysis of bundled SWCNT interconnects,” Journal of Semiconductor, vol. 36, no. 5, p. 055002, May 2015.
  • Vobulapuram Ramesh Kumar, Brajesh Kumar Kaushik, and A. Patnaik, " Crosstalk noise modeling of multiwall carbon nanotube (MWCNT) interconnects using Finite-difference time-domain (FDTD) technique," Microelectronics Reliability, vol. 55, no. 1, pp. 155-163, 2015.
  • V. Ramesh KumarManoj Kumar Majumder, Arsalan Alam, Narasimha Reddy K., and Brajesh Kumar Kaushik, “Stability and delay analysis of multi-layered GNR and multi-walled CNT interconnects,” Journal of Computational Electronics, Springer, vol. 14, no. 2, pp. 611-618, June 2015.
  • Pankaj Kr. Pal, Brajesh Kumar Kaushik, and S. Dasgupta, “Asymmetric dual-spacer tri-gate (ADS-TG) FinFET device-circuit co-design and its variability analysis,” IEEE Transactions on Electron Devices, vol.62, no.4, pp.1105-1112, Apr. 2015. 
  • Vobulapuram Ramesh Kumar, Manoj Kumar Majumder, Narasimha Reddy Kukkam, and Brajesh Kumar Kaushik, “Time and Frequency Domain Analysis of MLGNR Interconnects,” IEEE Transactions on Nanotechnology, vol. 14, no. 3, pp. 484-492, Mar. 2015.
  • Manoj Kumar Majumder, Jainender Kumar, and Brajesh Kumar Kaushik, “Process induced delay variation in SWCNT, MWCNT and Mixed CNT interconnects,” IETE Journal of Research, 2015, DOI: 10.1080/03772063.2015.1025110.

Year - 2014

  • Pankaj Kr. Pal, B. K. Kaushik, and S. Dasgupta, “Investigation of symmetric dual-k spacer trigate FinFETs from delay perspective,” IEEE Transactions on Electron Devices, vol.61, no.11, pp.3579-3585, Nov. 2014
  • Brajesh Kumar Kaushik, Manoj Kumar Majumder, and V. Ramesh Kumar, “Carbon Nanotube Based 3-D Interconnects – A Reality or a Distant Dream,” IEEE Circuits and Systems Magazine, vol. 14, no. 4, pp. 16-35, Nov., 2014.
  • Vobulapuram Ramesh Kumar, Manoj Kumar Majumder, and Brajesh Kumar Kaushik, “Graphene Based On-Chip Interconnects and TSVs – Prospects and Challenges,” IEEE Nanotechnology Magazine, vol. 8, no. 4, pp. 14-20, Dec. 2014.
  • Manoj Kumar Majumder, Brajesh Kumar Kaushik, and Sanjeev Kumar Manhas, “Analysis of Delay and Dynamic Crosstalk in Bundled Carbon Nanotube Interconnects,” IEEE Transactions on Electromagnetic Compatibility, 2014 (DOI: 10.1109/TEMC.2014.2318017).
  • Shivam Verma, Shalu Kaundal, and B. K. Kaushik, “Novel 4F2 Buried Source Line STT MRAM Cell with Vertical GAA Transistor as Select Device,” IEEE Trans. on Nanotechnology, vol. 13, no. 6, pp. 1163–1171, 2014.
  • Manoj Kumar Majumder, Jainender Kumar, V. Ramesh Kumar, and Brajesh Kumar Kaushik, “Performance analysis for randomly distributed mixed CNT bundle interconnects,” IET Micro & Nano Letters, vol. 9, no. 11, pp. 792-796, 2014.
  • Manoj Kumar Majumder, Pankaj Kumar Das, and Brajesh Kumar Kaushik, “Delay and Crosstalk Reliability Issues in Mixed MWCNT Bundle Interconnects,” Microelectronics Reliability, Elsevier, vol. 54, no. 11, pp. 2570-2577, 2014 (DOI: 10.1016/j.microrel.2014.04.008).
  • Manoj Kumar Majumder, Narasimha Reddy K., and Brajesh Kumar Kaushik, “Frequency Response and Bandwidth Analysis of MLGNR and MWCNT Interconnects,” IET Micro & Nano Letters, vol. 9, no. 9, pp. 557-560, 2014.
  • Pankaj Kumar Das, Manoj Kumar Majumder, and Brajesh Kumar Kaushik, “Dynamic Crosstalk Analysis of Mixed Multi-walled Carbon Nanotube Bundle Interconnects,” IET - The Journal of Engineering, 2014 (DOI: 10.1049/joe.2013.0272).
  • Narasimha Reddy K., Manoj Kumar Majumder and Brajesh Kumar Kaushik, “Delay Uncertainty in MLGNR Interconnects Under Process Induced Variations of Width, Doping, Dielectric Thickness and Mean Free Path,” Journal of Computational Electronics, Springer, vol. 13, no. 3, pp. 639-646, May 22, 2014 (DOI: 10.1007/s10825-014-0582-z).
  • Brijesh Kumar, B. K. Kaushik, and Y. S. Negi, “Static and dynamic characteristics of dual gate organic TFT based NAND and NOR circuits,” Journal of Computational Electronics, Springer, vol. 13, no. 3, pp 627-638, Feb. 2014.
  • Brijesh Kumar, B. K. Kaushik, and Y. S. Negi, “Design and analysis of noise margin, write ability and read stability of organic and hybrid 6-T SRAM cell,” Microelectronics Reliability, Elsevier, vol. 54, no. 12, pp. 2801-2812, 2014. 
  • Pankaj Kr. Pal, B. K. Kaushik, and S. Dasgupta, “Design metrics improvement for SRAMs using symmetric dual-k spacer (SymD-k) FinFETs,” IEEE Trans. on Electron Devices, vol. 61, no. 4, pp. 1123-1130, Apr. 2014 (Impact factor: 2.062).
  • Shivam Verma, Shalu Kaundal, B. K. Kaushik, “Modeling of in-plane magnetic tunnel junction for mixed mode simulations,” IEEE Trans. on Magnetics, 2014 (Impact factor: 1.422).
  • V. Ramesh Kumar, B. K. Kaushik, and A. Patnaik, "An accurate model for dynamic crosstalk analysis of CMOS gate driven on-chip interconnects using FDTD method," Microelectronics Journal, Elsevier (Impact factor: 0.912).
  • V. Ramesh Kumar, B. K. Kaushik, and A. Patnaik, "An accurate FDTD model for crosstalk analysis of CMOS gate driven coupled RLC interconnects," IEEE Trans. on Electromagnetic Compatibility, (Impact factor: 1.327).
  • Brijesh Kumar, B. K. Kaushik, and Y. S. Negi, “Organic thin film transistors: Structures, models, materials, fabrication and applications- A review”, Polymer Reviews, Taylor and Francis, vol. 54, no. 1, pp. 33–111, Feb. 2014 (Impact factor: 7.794).
  • Brijesh Kumar, B. K. Kaushik, and Y. S. Negi, “Analysis of electrical parameters of organic thin film transistors based on thickness variation in semiconducting and dielectric layers,” IET Circuits, Devices & Systems, vol. 8, no. 2, pp. 131–140, Jan. 2014 (Available on IEEE Explore, Impact Factor: 0.547).
  • Brijesh Kumar, B. K. Kaushik, Y. S. Negi and V. Goswami, “Single and dual gate OTFT based robust organic digital design,” Microelectronics Reliability, Elsevier, vol. 54, no. 1, pp. 100-109, Jan. 2014 (Impact Factor: 1.137).
  • Manoj Kumar Majumder, Archana Kumari, B. K. Kaushik, and S. K. Manhas, “Signal Integrity Analysis in Carbon Nanotube Based Through-Silicon Via,” Active and Passive Electronic Components, Hindawi, vol. 2014, Article ID 524107, pp. 1-7, 2014.
  • D. K. Sharma, B. K. Kaushik and R. K. Sharma, "Delay model for dynamically switching coupled RLC interconnects", European Physical Journal Applied Physics (EPJAP), 2014 (Impact Factor: 0.710).
  • D. K. Sharma, B. K. Kaushik and R. K. Sharma, “FDTD based transition time dependent crosstalk analysis for coupled RLC interconnects,” Journal of Semiconductors, IOP Publication, China, 2014.
  • Devendra Kumar Sharma, B. K. Kaushik and R. K. Sharma, “Delay model for dynamically switching coupled on-chip interconnects,” Journal of Engineering, Design and Technology, Emerald, U.K, 2014.
  • D. K. Sharma, B. K. Kaushik, and R. K. Sharma, “Signal integrity and propagation delay analysis using FDTD technique for VLSI interconnects,” Journal of Computational Electronics, Springer, vol. 13, no. 1, pp. 300-306, 2014 (Impact Factor: 1.013).
  • Brijesh Kumar, B. K. Kaushik, and Y. S. Negi, “Perspectives and challenges for organic thin film transistors: Materials, devices, processes and applications”, Journal of Material Science: Materials in Electronics, Springer, vol. 25, no. 1, pp. 1–30, 2014 (Impact Factor: 1.486).

Year - 2013

  • Pankaj Kr. Pal, B. K. Kaushik, and S. Dasgupta, “High-performance and robust SRAM cell based on asymmetric dual-k spacer Fin-FETs,” IEEE Transactions on Electron Devices, vol. 60, no. 10, Oct. 2013 (Impact factor: 2.062).
  • Brijesh Kumar, B. K. Kaushik, and Y. S. Negi, “Static and dynamic analysis of organic and hybrid inverter circuits,” Journal of Computational Electronics, Springer, vol. 12, no. 4, pp. 765–774, Dec. 2013 (Impact Factor: 1.013).
  • V. Goswami, Brijesh Kumar, B. K. Kaushik, Y. S. Negi, and K. L. Yadav, “Analysis of static and dynamic performance of organic inverter circuits based on dual and single gate OTFTs,” IET Circuits, Devices & Systems, vol. 7, no. 6, pp. 345–351, Nov. 2013 (Available on IEEE Explore, Impact Factor: 0.547).
  • S. K. Verma and B. K. Kaushik "Crosstalk Reduction using Bus Encoding in RLC Modeled Interconnects," European Journal of Scientific Research, vol. 110, no 1, Aug, 2013 106-118.
  • Brijesh Kumar, B. K. Kaushik, and Y. S. Negi, “Perspective and challenges for organic thin film transistors: Materials, devices, processes and applications,” Journal of Materials Science: Materials in Electronics, Springer, vol. 25, no. 1, pp. 1-30, Oct. 2013 (Impact Factor: 1.486).
  • Brijesh Kumar, B. K. Kaushik, Y. S. Negi, and V. Goswami, “Single and dual gate OTFTs based robust organic digital design,” Microelectronics Reliability, Elsevier, vol. 54, no. 1, pp. 100–109, Oct. 2013 (Impact Factor: 1.137).
  • Brijesh Kumar, B. K. Kaushik, Y. S. Negi, S. Saxena, and G. D. Varma, “Analytical modeling and parameter extraction of top and bottom contact structures of organic thin film transistors,” Microelectronics Journal, Elsevier, vol. 44, no. 9, pp. 736–143, Sep. 2013 (Impact Factor: 0.912).
  • Brijesh Kumar, B. K. Kaushik, and Y. S. Negi, “Modeling of top and bottom contact structure organic field effect transistors,” Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures, vol. 31, no. 1, pp. 012401-1–012401-7, Jan. 2013 (Published by AVS/ Available on IEEE Explore, SCI, Impact Factor: 1.597).
  • Brijesh Kumar, B. K. Kaushik, and Y. S. Negi, “Analysis of electrode thickness variation effect on performance parameters of polymer thin film transistor with device simulation,” Int. J. Advanced Intelligence Paradigms, vol. 5, no. 1/2, pp. 3–15, Jan. 2013.
  • Brijesh Kumar, B. K. Kaushik, and Y. S. Negi, “Influence of the contact thickness on electrical performance of staggered and planer p-channel organic field effect transistors,” Advanced Material Research, vol. 622-623, pp. 1434–1438, Dec. 2012.
  • B. K. Kaushik, D. Agarwal, and G. N. Babu, “Bus encoder design for reduced crosstalk, power and area in coupled VLSI interconnects,” Microelectronics Journal, Elsevier, vol. 44, no. 9, pp. 827-833, 2013 (Impact Factor: 0.912).
  • P. Mittal, Brijesh Kumar,, B. K. Kaushik, Y. S. Negi, and R. K. Singh, “Channel Length Variation Effect on Performance Parameters of Organic Field Effect Transistors,” Microelectronics Journal, Elsevier, vol. 43, no. 12, pp. 985-994, Aug. 2012 (Impact Factor: 0.912).
  • S. K. Verma, B. K. Kaushik, and S. K. Soni, “A low power novel encoding technique for RC modeled VLSI interconnects,” Journal of Low Power Electronics, American Scientific Publisher, vol. 9, no. 4, pp. 471-478, 2013 (Impact Factor: 0.485).
  • D. K. Sharma, B. K. Kaushik, and R. K. Sharma, “Effect of coupling parasitics and CMOS driver width on transition time for dynamic inputs,” International Journal of Electronics, Taylor & Francis, 2013 (Impact Factor: 0.509).
  • Devendra Kumar Sharma, B. K. Kaushik and R. K. Sharma, “Impact of driver size and interwire parasitics on crosstalk noise and delay,” Journal of Engineering, Design and Technology, Emerald, U.K., 2013.
  • S. K. Singh, B. K. Kaushik, and D. S. Chauhan, “A novel approach to reduce sub threshold leakage in deep sub-micron SRAM,” World Applied Sciences Journal, vol. 22, no. 3, pp. 442-446, 2013.
  • Y. S. Duksh, B. K. Kaushik, S. Sarkar, and R. Singh, “Analysis of propagation delay and power with variation in driver size and number of shells in multi walled carbon nanotube interconnects,” Journal of Engineering, Design and Technology, Emerald, vol. 11, no. 1, pp. 19-33, 2013.
  • Manoj Kumar Majumder, B. K. Kaushik, and S. K. Manhas, “Novel Spatially Arranged Mixed Carbon Nanotube Bundle Interconnects – Impact on Delay and Power,” Scientia Iranica Transactions F: Nanotechnology, vol. 20, no. 6, pp. 2341-2347, Jul. 2013.
  • Manoj Kumar Majumder, Nisarg D. Pandya, B. K. Kaushik, and S. K. Manhas, “Signal Integrity Analysis in Single and Bundled Carbon Nanotube Interconnects,” Journal of Nanoscience, Hindawi, vol. 2013, no. 407301, pp. 1-6, 2013.
  • S.K. Singh and B. K. Kaushik, “A novel approach to reduce leakage current in ULP SRAM,” IETE Journal of Research, vol. 59, no. 6, pp. 704-708, 2013.
  • S. K. Singh, B. K. Kaushik, D. S. Chauhan, and S. Kumar, “Reduction of subthreshold leakage current in MOS transistors,” World Applied Sciences Journal, vol. 25, no. 3, pp. 446-450, 2013.

Year - 2012

  • M. K. Majumder, N. D. Pandya, B. K. Kaushik, and S. K. Manhas, “Analysis of MWCNT and Bundled SWCNT Interconnects: Impact on Crosstalk and Area,” IEEE Electron Device Letters, vol. 33, no. 8, pp. 1180-1182, Aug. 2012 (Impact Factor: 2.789).
  • M. K. Majumder, N. D. Pandya, B. K. Kaushik, and S. K. Manhas, “Dynamic Crosstalk Effect in Mixed  CNT Bundle Interconnects,” Electronics Letters, vol. 48, no.7, pp. 384-385, Mar. 29, 2012 (Published by IET/Available on IEEE Explore, Impact Factor: 1.038).
  • Poornima Mittal, Brijesh Kumar, B. K. Kaushik, Y. S. Negi and R. K Singh, “Channel length variation effect on performance parameters of organic field effect transistors, Microelectronics Journal, Elsevier, vol. 43, no. 12, pp. 985–994, Dec. 2012 (Impact Factor: 0.912).
  • Poornima Mittal, Brijesh Kumar, B. K. Kaushik, Y. S. Negi and R. K Singh, “Analysis of pentacene based organic thin film transistors through two dimensional finite element dependent numerical device simulation,” International Journal of Computer Application (IJCA), vol. 3 (OOC-1): pp. 11–17, 2012.
  • Devendra Kumar Sharma, B. K. Kaushik and R. K. Sharma, “Effect of equal and mismatched signal transition time on power dissipation in global VLSI interconnects,” International Journal of VLSI Design & Communication Systems, vol. 3, no. 4, Aug. 2012.
  • S. K. Verma and B. K. Kaushik, “A Bus Encoding Method for Crosstalk and Power Reduction in RC Coupled VLSI Interconnects,” International Journal of VLSI design & Communication Systems (VLSICS), vol. 3, no. 2, pp. 29-39, 2010.

Year - 2011

  • D. K. Sharma, R. K. Sharma, B. K. Kaushik, and P. Kumar, “Boundary scan based testing algorithm to detect interconnect faults in printed circuit boards,” Circuit World, Emerald, vol. 37, no. 3, pp. 27-34, 2011 (Impact Factor: 0.683).
  • B. K. Kaushik, Rajendra P. Agarwal, Sankar Sarkar, Ramesh C. Joshi, and D. S. ChauhanRepeater insertion in crosstalk-aware inductively and capacitively coupled interconnects” International Journal of Circuit Theory and Applications, Wiley, vol. 39, no. 6, pp.629-647, Jun. 2011 (Impact Factor: 1.293).
  • D. K. Sharma, B. K. Kaushik, and R. K. Sharma, “VLSI Interconnects and their Testing- Prospects and Challenges Ahead,” Journal of Engineering, Design and Technology, Emerald, UK, vol. 9, no. 1, pp. 63-84, 2011.
  • Neha Jain, B. K. Kaushik, B. Jharia, and R. P. Agarwal  “Design of a High Speed, Low Power and Area Efficient MAC for VLSI-DSP Chip,” Journal of Active and Passive Electronic Devices, USA, vol. 6, no. 3/4, pp. 333-339, 2011.
  • Manoj Kumar Majumder, B. K. Kaushik, and S. K. Manhas, “A Comparative Study of SWNT Bundle and MWNT in Terms of Area and Propagation Delay for Global Interconnects,” International Journal of Contemporary Research in Engineering and Technology, vol. 1, no. 1, pp. 45-60, Dec. 2011.
  • Manoj Kumar Majumder, B. K. Kaushik, and S. K. Manhas, “A Comparative Analysis of Single Walled CNT Bundle and Multi Walled CNT as Future Global VLSI Interconnects,” International Journal of Computer Applications (IJCA) Special Issue on Evolution in Networks and Computer Communications, vol. 2, no. 6, pp. 32-38, Oct. 11, 2011.

Year - 2010

  • B. K. Kaushik, S. Sarkar, R. P. Agarwal, and R. C. Joshi, “An analytical approach to dynamic crosstalk in coupled interconnects” Microelectronics Journal, Elsevier, vol. 41, no. 2-3, pp. 85-92, 2010 (Impact Factor: 0.912).
  • Yograj Singh Duksh, Brajesh Kumar Kaushik, Sankar Sarkar, Raghuvir Singh, "Performance comparison of carbon nanotube, nickel silicide nanowire and copper VLSI interconnects: Perspectives and challenges ahead", Journal of Engineering, Design and Technology, Emerald, U.K., vol. 8, no. 3, pp.334 – 353, 2010.
  • Manoj Gupta, Brajesh Kumar Kaushik and Laxmi Chand “Performance of Bilinear Transformation in Audio Algorithm Implementation and Optimization on Processor,” International Journal of Recent Trends in Engineering [ISSN 1797-9617], Academy Publishers, Finland, 2010, vol. 3, no. 4, pp. 38-41.
  • S. K. Verma and B. K. Kaushik “Encoding Schemes for the Reduction of Power Dissipation, Crosstalk and Delay: A Review,” International Journal of Recent Trends in Engineering [ISSN 1797-9617], Academy Publishers, Finland, 2010, vol. 3, no. 4, pp. 74-79.
  • Divya Mishra, Shailendra Mishra, Praggya Agnihotry and B. K. Kaushik “Crosstalk Scenario in Multiline VLSI Interconnects,” International Journal of Recent Trends in Engineering [ISSN 1797-9617], Academy Publishers, Finland, 2010, vol. 3 no. 4, pp. 80-83.
  • Amritkar Mandal and Brajesh Kumar Kaushik, “CORDIC-Based VLSI Architecture for Adaptive Decision Feedback Equalizer,” International Journal of Micro and Nano Electronics, Circuits and Systems, vol. 2, iss 2, pp. 179-183, 2010.
  • Divya Mishra, Shailendra Mishra, Praggya Agnihotry and B. K. Kaushik, “Effect of Distributed Shield Insertion on Crosstalk in Inductively Coupled VLSI Interconnects” Journal of Computer Science and Engineering, vol. 1, iss. 1, May 2010, pp. 77-81.

Year - 2009

  • Brajesh Kumar Kaushik, Sankar Sarkar, Rajendra P. Agarwal, and Ramesh C. Joshi, “Crosstalk Analysis of Simultaneously Switching Interconnects” International Journal of Electronics, Taylor and Francis (UK), Vol. 96, No.10, pp. 1095-1114, Oct. 2009 (Impact Factor: 0.509).
  • K. G. Verma, B. K. Kaushik, and R. Singh, “Effects of Process Variation in VLSI Interconnects- a Technical Review” Microelectronics International, Emerald Pub. U.K., vol. 26, no. 3, pp. 49-55, 2009 (Impact Factor: 0.731).
  • Viplove Goel, Anil Chauhan, Shailesh Goswami, Rohit Bankoti and B. K. Kaushik, “Roadmap to Radio Frequency Identification and Library Implementation: A Review and Case Study” International Journal of Computer Science and Management Systems (IJCSMS), vol. 1, no. 1, pp. 37-43, Jun. 2009.
  • K. G. Verma, B. K. Kaushik and R. Singh, “Interconnect Based Process Variation in VLSI” International Journal of Computer Science and Management Systems (IJCSMS), vol. 1, no. 1, pp. 19-26, Jun. 2009.
  • Ittee Teli and B. K. Kaushik, “Demodulation of Advance Technique in Differential Binary Phase Shift Keying” International Journal of Scientific Computing (IJSC), ISSN: 0973-578X, vol. 3, no. 1, Jan-Jun. 2009, pp.173-178.
  • Jitendra Kumar Verma, B. K. Kaushik and Kirat Pal, “Design and Simulation of Components of a New Digital Phase Locked Loop (PLL) on 0.18µm CMOS Technology” International Journal on Information and Communication Technologies (IJICT), ISSN: 0973-5836, vol. 2, no. 1-2, Jan-Jun. 2009, pp. 167-171.
  • Shakti Manchanda, B. K. Kaushik, and C. K. Joshi “High Resolution Chirp Generator for FMCW Ladar” International Journal of Scientific Computing (IJSC), ISSN: 0973-578X, vol. 3, no. 1, Jan-June 2009, pp.29-32.
  • Brajesh Kumar Kaushik, Sankar Sarkar, Rajendra P. Agarwal, and Ramesh C. Joshi, “Crosstalk Analysis of Simultaneously Switching Interconnects,” International Journal of Electronics, Taylor and Francis (UK), vol. 96, no.10, Oct. 2009, pp. 1095-1114 (Impact Factor: 0.509).
  • K. G. Verma, B. K. Kaushik and R.Singh, “Effects of Process Variation in VLSI Interconnects- a Technical Review,” Microelectronics International, Emerald Pub. U.K., vol. 26, no. 3, 2009, pp. 49-55 (Impact Factor: 0.731).

Year - 2008

  • Brajesh Kumar Kaushik and Sankar Sarkar, “Crosstalk Analysis for a CMOS Gate Driven Coupled VLSI Interconnects”, IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, vol. 27, no. 6, pp. 1150-1154, Jun. 2008 (Impact Factor: 1.093).
  • Brajesh Kumar Kaushik and Sankar Sarkar, “Crosstalk Analysis for a CMOS Gate Driven Inductively and Capacitively Coupled Interconnects”, Microelectronics Journal, Elsevier, vol. 38, pp. 1834– 1842, 2008 (Impact Factor: 0.912).

Year - 2007

  • Brajesh Kumar Kaushik, Sankar Sarkar and R.P.Agarwal, “Waveform Analysis and Delay Prediction for a CMOS Gate Driving RLC Interconnect Load”, Integration, the VLSI Journal, Elsevier Pub., Netherlands, vol. 40, no. 4, pp. 394-405, Jul. 2007 (Impact Factor: 0.452).
  • Brajesh Kumar Kaushik, Saurabh Goel and Gaurav Rauthan, “Future VLSI Interconnects: Optical Fiber or Carbon Nanotube – a Review” Microelectronics International, Emerald Pub., U.K., vol. 24, no. 2, pp.53 – 63, Apr. 2007 (Impact Factor: 0.731).
  • B. K. Kaushik, S. Sarkar, R. P. Agarwal, and R. C. Joshi, “Voltage scaling - A novel approach for crosstalk reduction in global VLSI interconnects,” Microelectronics International, Emerald Pub., U.K., vol. 24, no. 1, pp. 40 – 45, 2007 (Impact Factor: 0.731).
  • Brajesh Kumar Kaushik, Sankar Sarkar, Rajendra P. Agarwal, and Ramesh C. Joshi, “Effect of Line Resistance and Driver Width on Crosstalk in Coupled VLSI Interconnects” Microelectronics International, Emerald Pub. U.K., vol. 24, no. 3, pp. 42-45, Aug. 2007 (Impact Factor: 0.731).
  • Brajesh Kumar Kaushik, Sankar Sarkar, Rajendra P. Agarwal, and Ramesh C. Joshi, “Crosstalk Reduction by Voltage Scaling in Global VLSI Interconnects” Journal of Active and Passive Devices, USA, vol. 2, no. 3, pp.199-221, 2007.

Year - 2006

  • Brajesh Kumar Kaushik, S.Sarkar and R.P.Agarwal, “Width Optimization of Global Inductive VLSI interconnects” Microelectronics International, Emerald Pub. U.K., vol. 23, no. 1, pp. 26–30, Feb. 2006 (Impact Factor: 0.731).
  • B. K. Kaushik, S. Sarkar and R. P. Agarwal, “Crosstalk Aware Repeater Insertion for Coupled VLSI Interconnects” International Journal of Systemics, Cybernetics and Informatics (IJSCI), Pentagram Pub., India pp. 22-27, April 2006.            
  • Brajesh Kumar Kaushik, S. Sarkar, R. P. Agarwal and R. C. Joshi, “Crosstalk Analysis and Repeater Insertion in Crosstalk Aware Coupled VLSI Interconnects”, Microelectronics International, Emerald Pub., U.K., vol. 23, no. 3, pp. 55-63, Aug 2006 (Impact Factor: 0.731).