Areas of Interest
- VLSI Circuit and System Level Designs, Cyber Physical System Designs and FPGA based Designs., Standard Cell library Design, Resilient circuit design, Hardware security, Variability Measurement
Professional Background
| From | To | Position | Organisation |
|---|---|---|---|
| 2012-01-01 | 2013-01-01 | Post Doctoral Researcher | CMU, Pittsburgh, USA |
| 2009-01-01 | 2012-01-01 | Post Doctoral Researcher | Kyoto University, Japan |
Honors and Awards
| Award | Institute | Year |
|---|---|---|
| Young Faculty Research Fellowship (YFRF) | Ministry of Electronics &: Information Technology (MeitY), Government of India | 2018 |
Educational Details
| Degree | Subject | University | Year |
|---|---|---|---|
| Ph.D. | Electronics Design & Technology | IISc, Bangalore | 2009 |
Sponsored Research Projects
| Topic | Funding Agency | Start Date | Period |
|---|---|---|---|
| Design and on-chip characterization of standard cell library | FIG | 2015-01 | 5 years 8 months |
| Design of Voltage-Scalable and Process Variation Tolerant Standard Cell Library | SERB | 2016-01 | 4 years 8 months |
| SMDP C2SD (Chips to Systems Design) | MEITY | 2015-01 | 5 years 8 months |
Teaching Engagements
| Title | Course Code | Class Name | Semester |
|---|---|---|---|
| Analog VLSI Circuit Design | ECN-581 | M.Tech., B.Tech IV, Ph.D | Autumn |
| VLSI Physical Design | ECN-591 | M.Tech., B.Tech IV, Ph.D | Spring |
| Digital System Design | ECN-578 | M.Tech., B.Tech IV, Ph.D | Autumn |
| IC Application Laboratory | ECN-351 | B.Tech III | Autumn |
| Digital Electronic Circuits Laboratory | ECN-252 | B.Tech II | Spring |
| Microelectronic Devices,Technology and Circuits | ECN-341 | B.Tech III | Autumn |
| Training and Seminar | EC-491 | B.Tech IV | Autumn |
| DIGITAL LOGIC DESIGN | ECN-104 | BTech (CSE) | Spring |
| Digital Logic Design | ECN-104 | BTech (CSE) | Spring |
PHDs Supervised
| Topic | Scholar Name | Status of PHD | Registration Date |
|---|---|---|---|
| Resilient Circuit Design | Sannena Govinda | O | 2014-01 |
| Sub-threshold Standard Cell Design | Priyamvada Sharma | O | 2014-01 |
| On-chip Process Variation Measurement | Poorvi Jain | O | 2015-01 |
| Memory Design | Prasanna Kumar Saragada | O | 2017-01 |
| DSP architectures | Anu Verma | O | 2018-01 |
| RF Circuit Design | Anshul Verma | O | 2019-01 |
| Soil Sensors | Aranya Gupta | O | 2020-01 |
Books Authored
1. Bishnu Prasad Das, Bharadwaj Amrutur and Hidetoshi Onodera, “On-chip gate delay variability measurement in scaled technology node", in Book title: Nano-CMOS and Post-CMOS Electronics: Vol 2. Circuits and Design, Edited by S. P. Mohanty and A. Srivastava, The Institute of Engineering and Technology (IET), UK, 2015, ISBN: 978-1-84919-999-5.
Available : http://www.theiet.org/resources/books/circuits/Ncmosvol2.cfm
Refereed Journal Papers
Patent
P1. Bharadwaj Amrutur and Bishnu Prasad Das, “Gate Delay Measurement Circuit and Method of Determining a Delay of a Logic Gate” US patent No. 8,224,604 B1 and date of Patent July 17, 2012.
P2. Lawrence Pileggi, Bishnu P. Das, Kaushik Vaidyanathan, “Testing integrated circuits during split fabrication,” Application No: PCT/US2015/012220, Publication no: WO2015160405 A3, Publication date, Dec 10, 2015.
Journal Papers
J8. Poorvi Jain and Bishnu Prasad Das, "On-Chip Threshold Voltage Variability Estimation Using Reconfigurable Ring Oscillator, "Accepted in IEEE Transactions on Semiconductor Manufacturing.
J7. Govinda Sannena and Bishnu Prasad Das, "Low Overhead Warning Flip-flop Based on Charge Sharing for Timing Slack Monitoring," in IEEE Transactions on Very Large Scale Integration Systems (Accepted For Publication).
J6. Govinda Sannena and Bishnu Prasad Das, "Metastability immune and area efficient error masking flip-flop for timing error resilient designs", in Elsevier Integration, the VLSI Journal (Accepted For Publication).
J5. Bishnu Prasad Das and Hidetoshi Onodera, “Frequency-Independent Warning Detection Sequential for Dynamic Voltage and Frequency Scaling in ASICs,” in IEEE Transactions on Very Large Scale Integration Systems, vol. 22, no. 12, pp. 2535-2548, Dec. 2014.
J4. Bishnu Prasad Das and Hidetoshi Onodera, “On-chip Measurement of Rise/Fall Gate Delay Using Reconfigurable Ring Oscillator,” IEEE Transactions on Circuits and Systems II, Vol. 61, No. 3, Mar 2014, pp. 183-187.
J3. Bishnu Prasad Das and Hidetoshi Onodera, “Area-Efficient Reconfigurable-Array-Based Oscillator for Standard Cell Characterization,” IET Circuits Devices Syst., Vol. 6, Iss. 6, pp. 429–436, Nov. 2012.
J2. Bishnu Prasad Das, Bharadwaj Amrutur, H.S.Jamadagni, N.V.Arvind, V. Visvanathan, “Voltage and Temperature Aware SSTA Using Neural Network Delay Model,” IEEE Transactions on Semiconductor Manufacturing, vol. 24, No. 4, pp. 533- 544, Nov. 2011.
J1. Bishnu Prasad Das, Bharadwaj Amrutur, H.S.Jamadagni, N.V.Arvind, V. Visvanathan, “Within-Die Gate Delay Variability Measurement using Re-configurable Ring Oscillator,” IEEE Transactions on Semiconductor Manufacturing, Vol. 22, No. 2, pp. 256-267, May 2009.
Conference papers
C17. Poorvi Jain and Bishnu Prasad Das, "On-Chip Threshold Voltage Variability Detector Targeting Supply of Ring Oscillator for Characterizing Local Device Mismatch", Accepted in ICMTS conference 2019 at Kita-kyushu City, Japan
C16. Swaati and Bishnu Prasad Das, " A 10T Subthreshold SRAM Cell with Minimal Bitline Switching for Ultra-low Power Applications", 21st International Symposium on VLSI Design and Test (VDAT), 2017, Roorkee, India.
C15. Poorvi Jain and Bishnu Prasad Das, "Within-Die Threshold Voltage Variability Estimation Using Reconfigurable Ring Oscillator", IEEE VLSI Design conference, 2017, Hyderabad, India.
C14. Govinda Sannena and Bishnu Prasad Das, "Area and Power-efficient Timing Error Predictor for Dynamic Voltage and Frequency Scaling Application," IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), December 19-21, 2016, Gwalior, India
C13. Govinda Sannena and Bishnu Prasad Das, "A Metastability Immune Timing Error Masking FlipFlop for Dynamic Variation Tolerance," ACM GLSVLSI, Boston, USA, May, 2016.
C12. Kaushik Vaidyanathan, Bishnu P Das and Larry Pileggi, “Detecting Reliability Attacks during Split Fabrication using Test-only BEOL Stack,” IEEE/ACM Design Automation Conference (DAC), June, 2014
C11. Kaushik Vaidyanathan, Bishnu P Das, Ekin Sumbul, Renzhi Liu, Larry Pileggi, “Building trusted ICs using split fabrication,” IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), 2014
C10. Bishnu Prasad Das and Hidetoshi Onodera, “Reconfigurable Array-Based Area-Efficient Test Structure for Standard Cell Characterization,” IEEE Twelfth Workshop on RTL and High Level Testing, 2011.
C9. Bishnu Prasad Das and Hidetoshi Onodera, “Warning Prediction Sequential for Transient Error Prevention,” IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems 2010.
C8. Bishnu Prasad Das and Hidetoshi Onodera, “Accurate Individual Gate Delay Measurement to Study Within-die Variations”, IEICE Spring meeting, Sendai, Japan, March 2010
C7. Bishnu Prasad Das, “Delay Variability: Modeling and On-chip Measurement”, PhD Forum, Design Automation & Test in Europe, Nice, France, April, 2009
C6. Bishnu Prasad Das, Bharadwaj Amrutur, H.S.Jamadagni, N.V.Arvind, V. Visvanathan, “Within-Die Gate Delay Variability Measurement using Re-configurable Ring Oscillator”, IEEE Custom Integrated Circuits Conference (CICC), San Jose, USA, September 2008.
C5. Bishnu Prasad Das, Janakiraman V, B Amrutur, H.S. Jamadagni, N.V. Arvind, “Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations”, IEEE VLSI Design Conference, Hyderabad, India, Jan 2008
C4. Janakiraman V, Bishnu Prasad Das, B Amrutur, “Voltage and temperature scalable standard cell leakage models based on stacks for statistical leakage characterization”, IEEE VLSI Design Conference, Hyderabad, India, Jan 2008.
C3. Bishnu Prasad Das, Bharadwaj Amrutur, H S Jamadagni “Voltage scalable statistical gate delay models using neural networks”, 11th IEEE VLSI Design And Test Symposium, Kolkota, India, 2007.
C2. Janakiraman, Bishnu Prasad Das, Vish Visvanathan and B. Amrutur, "Leakage modeling of logic gates considering effect of input vectors", 11th IEEE VLSI Design And Test Symposium, Kolkota, India, 2007
C1. Bishnu Prasad Das, Bharadwaj Amrutur, H.S.Jamadagni, “Critical Path Modeling for Dynamic Voltage Scaling (DVS) in Low Power Applications”, 10th IEEE VLSI Design and Test Symposium, Goa, India, 2006.
