VDAT 2017
Indian Institute of Technology Roorkee
29th June - 2nd July 2017

IIT Roorkee in association with IEEE UP Section and VSI presents
21st International Symposium on VLSI Design and Test
 (VDAT 2017)

INSPIRING INNOVATIONS

29th JUNE - 2nd JULY 2017
IIT Roorkee, INDIA




Click here to Submit your paper
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ABOUT THE SYMPOSIUM

VLSI Design and test VDAT is a flagship event of the VLSI Society of India. This Symposium follows successful organization of twenty symposiums in previous years. VDAT -2017 is being organized at Indian Institute of Technology Roorkee, India. In true sense, VDAT-2017 is a focused research event encompassing themes related to various disciplines of VLSI. The objective of the symposium is to bring professional engineers, academicians and research scholars of matching interests on a common platform to share new ideas, experiences, and knowledge in various fields of VLSI Design, Test and Technology. The scientific program will consist of peer-reveiwed paper presentations in parallel technical sessions. In addition, keynote lectures, presentation by industry professionals, panel discussions, tutorials and poster presentation will be conducted during the conference. Such interactions will faciliate better understanding about technological developments all across the globe amongst the peers. This conference will certainly ignite the minds of the researchers for undertaking more interdisciplinary collaborative research for up gradation of technology.
Papers are invited in the following topics of focus (but not limited to)....
1.) Device - Circuit Interactions  
  • Digital / Analog Circuits.  
  • Technology - circuits Co-Design. 
  • Impact of Novel Device Structure/ phenomena on Circuits. 
  • Device Modeling and Simulation. 
  • Multi-gate/ FDSOI device-circuit interaction. 
  
2.) VLSI Design  
  • CMOS Analog, Mixed-Signal and digital circuits. 
  • Circuit timing and power models. 
  • Low Power and near/sub threshold circuit design. 
  • Analog, Mixed-Signal and digital system design. 
  • Reconfigurable logic/computation. 
  • Design for manufacturability. 
  
3.) Emerging Technologies 
  • MeMs / NeMs. 
  • Organic Electronic. 
  • Spintronics. 
  • 2-D material electronics. 
  • Device physics design and circuits using non- silicon materials. 

4.) CAD for VLSI 
 
  • Logic and behavioral synthesis. 
  • Placement, routing and floorplanning. 
  • CAD tools. 
  • Design Automation.  

5.) Testing and Verification 
  • Design Verification, Test, Reliability and Fault Tolerance.  
  • Formal Verification. 
  • DFT. 
  • Fault Modeling. 
  • Post-silicon Validation. 
  • Testing memories and regular logic arrays. 
  • Design for manufacturability and yield analysis.
SPEAKERS
SPEAKER DESCRIPTION
Registrations are open. Please CLICK HERE to submit your paper. 
 
Please Note: IEEE/ VSI Student members are encouraged to participate and a 20% concession is being given to them. Apart from this, Fellowships will are be given to desrving candidates.



Regular Paper

Last Date for Paper Submission : 27th Feb, 2017    
Notification of Acceptance   : 25th Apr, 2017
Camera Ready Version          : 7th May, 2017  


Tutorials

Tutorial Proposal               :15th Mar, 2017  
Tutorial Announcement       :15th Apr, 2017


Work-in-progress (WIP) Forum
 
WIP Submission                 : 5th Mar, 2017  
Notification of Acceptance  : 15th Apr, 2017  
Camera Ready Version        25th Apr, 2017
IMPORTANT DATES
OUR SPONSORS
Companies are invited to become Sponsors of the International Symposium on VLSI Design and Test VDAT 2017.